4.8.2. Instruction and data cache operations by address

The cache maintenance operations by address registers are ICIMVAU, DCIMVAC, DCCMVAU, DCCMVAC, and DCCIMVAC. These registers are WO, reads return 0. See the register summary in Table 4.64 for their attributes. The bit assignments are:

Table 4.65. Cache operations registers bit assignments

[31:5]MVAWOMVA of requested operation

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