4.8.3. Data cache operations by set-way

The DCISW, DCCSW and DCCISW registers are WO. Reads return 0. See the register summary in Table 4.64 for their attributes. The bit assignments are:

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Table 4.66. Cache operations by set-way bit assignments


Way that operation applies to.

For the data cache, values 0, 1, 2 and 3 are supported.

[13:5]SetWOSet/index that operation applies to. The number of indices in a cache depends on the configured cache size. When this is less than the maximum, use the LSB of this field. The number of sets in the cache can be determined by reading the Cache Size ID Register.
[0]--Always reads as zero.

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