4.8.4. Accessing the Cortex-M7 NVIC cache maintenance operations using CMSIS

CMSIS functions enable software portability between different Cortex-M profile processors. To access cache maintenance operations when using CMSIS, use the following functions:

Table 4.67. CMSIS access cache maintenance operations

CMSIS function Descriptions
void SCB_EnableICache (void) Invalidate and then enable instruction cache
void SCB_DisableICache (void) Disable instruction cache and invalidate its contents
void SCB_InvalidateICache (void) Invalidate instruction cache
void SCB_EnableDCache (void) Invalidate and then enable data cache
void SCB_DisableDCache (void) Disable data cache and then clean and invalidate its contents
void SCB_InvalidateDCache (void)Invalidate data cache
void SCB_CleanDCache (void) Clean data cache
void SCB_CleanInvalidateDCache (void)Clean and invalidate data cache
void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)Invalidate data cache by address
void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)Clean data cache by address
void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)Clean and invalidate data cache by address

Arm might add more cache management functions to the CMSIS in the future, and recommends that you check the CMSIS documentation on a regular basis for the latest information.

Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C