Arm® Cortex®-M7 Devices Generic User Guide

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Typographical conventions
Additional reading
Feedback on content
1. Introduction
1.1. About the Cortex-M7 processor and core peripherals
1.1.1. System level interface
1.1.2. Integrated configurable debug
1.1.3. Cortex-M7 processor features and benefits summary
1.1.4. Cortex-M7 processor core peripherals
2. The Cortex-M7 Processor
2.1. Programmers model
2.1.1. Processor mode and privilege levels for software execution
2.1.2. Stacks
2.1.3. Core registers
2.1.4. Exceptions and interrupts
2.1.5. Data types
2.1.6. The Cortex Microcontroller Software Interface Standard
2.2. Memory model
2.2.1. Memory regions, types and attributes
2.2.2. Memory system ordering of memory accesses
2.2.3. Behavior of memory accesses
2.2.4. Software ordering of memory accesses
2.2.5. Memory endianness
2.2.6. Synchronization primitives
2.2.7. Programming hints for the synchronization primitives
2.2.8. Dynamic read allocate mode
2.3. Exception model
2.3.1. Exception states
2.3.2. Exception types
2.3.3. Exception handlers
2.3.4. Vector table
2.3.5. Exception priorities
2.3.6. Interrupt priority grouping
2.3.7. Exception entry and return
2.4. Fault handling
2.4.1. Fault types
2.4.2. Fault escalation and hard faults
2.4.3. Synchronous and Asynchronous bus faults
2.4.4. Fault status registers and fault address registers
2.4.5. Lockup
2.5. Power management
2.5.1. Entering sleep mode
2.5.2. Wakeup from sleep mode
2.5.3. The optional Wakeup Interrupt Controller
2.5.4. The optional external event input
2.5.5. Power management programming hints
3. The Cortex-M7 Instruction Set
3.1. Instruction set summary
3.1.1. Binary compatibility with other Cortex processors
3.2. CMSIS functions
3.3. About the instruction descriptions
3.3.1. Operands
3.3.2. Restrictions when using PC or SP
3.3.3. Flexible second operand
3.3.4. Shift Operations
3.3.5. Address alignment
3.3.6. PC‑relative expressions
3.3.7. Conditional execution
3.3.8. Instruction width selection
3.4. Memory access instructions
3.4.1. ADR
3.4.2. LDR and STR, immediate offset
3.4.3. LDR and STR, register offset
3.4.4. LDR and STR, unprivileged
3.4.5. LDR, PC‑relative
3.4.6. LDM and STM
3.4.7. PLD
3.4.8. PUSH and POP
3.4.9. LDREX and STREX
3.4.10. CLREX
3.5. General data processing instructions
3.5.1. ADD, ADC, SUB, SBC, and RSB
3.5.2. AND, ORR, EOR, BIC, and ORN
3.5.3. ASR, LSL, LSR, ROR, and RRX
3.5.4. CLZ
3.5.5. CMP and CMN
3.5.6. MOV and MVN
3.5.7. MOVT
3.5.8. REV, REV16, REVSH, and RBIT
3.5.9. SADD16 and SADD8
3.5.10. SHADD16 and SHADD8
3.5.11. SHASX and SHSAX
3.5.12. SHSUB16 and SHSUB8
3.5.13. SSUB16 and SSUB8
3.5.14. SASX and SSAX
3.5.15. TST and TEQ
3.5.16. UADD16 and UADD8
3.5.17. UASX and USAX
3.5.18. UHADD16 and UHADD8
3.5.19. UHASX and UHSAX
3.5.20. UHSUB16 and UHSUB8
3.5.21. SEL
3.5.22. USAD8
3.5.23. USADA8
3.5.24. USUB16 and USUB8
3.6. Multiply and divide instructions
3.6.1. MUL, MLA, and MLS
3.6.4. SMLAD and SMLADX
3.6.6. SMLSD and SMLSLD
3.6.7. SMMLA and SMMLS
3.6.8. SMMUL
3.6.9. SMUAD and SMUSD
3.6.10. SMUL and SMULW
3.6.12. SDIV and UDIV
3.7. Saturating instructions
3.7.1. SSAT and USAT
3.7.2. SSAT16 and USAT16
3.7.3. QADD and QSUB
3.7.4. QASX and QSAX
3.7.5. QDADD and QDSUB
3.7.6. UQASX and UQSAX
3.7.7. UQADD and UQSUB
3.8. Packing and unpacking instructions
3.8.1. PKHBT and PKHTB
3.8.2. SXT and UXT
3.8.3. SXTA and UXTA
3.9. Bit field instructions
3.9.1. BFC and BFI
3.9.2. SBFX and UBFX
3.9.3. SXT and UXT
3.10. Branch and control instructions
3.10.1. B, BL, BX, and BLX
3.10.2. CBZ and CBNZ
3.10.3. IT
3.10.4. TBB and TBH
3.11. Floating-point instructions
3.11.1. VABS
3.11.2. VADD
3.11.3. VCMP and VCMPE
3.11.4. VCVT and VCVTR between floating-point and integer
3.11.5. VCVT between floating-point and fixed-point
3.11.6. VCVTB and VCVTT
3.11.7. VDIV
3.11.8. VFMA and VFMS
3.11.9. VFNMA and VFNMS
3.11.10. VLDM
3.11.11. VLDR
3.11.12. VMLA and VMLS
3.11.13. VMOV Immediate
3.11.14. VMOV Register
3.11.15. VMOV Scalar to Arm Core register
3.11.16. VMOV Arm Core register to single-precision
3.11.17. VMOV two Arm Core registers to two single-precision registers
3.11.18. VMOV two Arm core registers and a double-precision register
3.11.19. VMOV Arm Core register to scalar
3.11.20. VMRS
3.11.21. VMSR
3.11.22. VMUL
3.11.23. VNEG
3.11.24. VNMLA, VNMLS and VNMUL
3.11.25. VPOP
3.11.26. VPUSH
3.11.27. VSQRT
3.11.28. VSTM
3.11.29. VSTR
3.11.30. VSUB
3.11.31. VSEL
3.11.32. VMAXNM and VMINNM
3.11.34. VRINTR and VRINTX
3.12. Miscellaneous instructions
3.12.1. BKPT
3.12.2. CPS
3.12.3. CPY
3.12.4. DMB
3.12.5. DSB
3.12.6. ISB
3.12.7. MRS
3.12.8. MSR
3.12.9. NEG
3.12.10. NOP
3.12.11. SEV
3.12.12. SVC
3.12.13. WFE
3.12.14. WFI
4. Cortex-M7 Peripherals
4.1. About the Cortex-M7 peripherals
4.2. Nested Vectored Interrupt Controller
4.2.1. Accessing the Cortex-M7 NVIC registers using CMSIS
4.2.2. Interrupt Set-enable Registers
4.2.3. Interrupt Clear-enable Registers
4.2.4. Interrupt Set-pending Registers
4.2.5. Interrupt Clear-pending Registers
4.2.6. Interrupt Active Bit Registers
4.2.7. Interrupt Priority Registers
4.2.8. Software Trigger Interrupt Register
4.2.9. Level-sensitive and pulse interrupts
4.2.10. NVIC design hints and tips
4.3. System control block
4.3.1. Auxiliary Control Register
4.3.2. CPUID Base Register
4.3.3. Interrupt Control and State Register
4.3.4. Vector Table Offset Register
4.3.5. Application Interrupt and Reset Control Register
4.3.6. System Control Register
4.3.7. Configuration and Control Register
4.3.8. System Handler Priority Registers
4.3.9. System Handler Control and State Register
4.3.10. Configurable Fault Status Register
4.3.11. HardFault Status Register
4.3.12. MemManage Fault Address Register
4.3.13. BusFault Address Register
4.3.14. System control block design hints and tips
4.4. System timer, SysTick
4.4.1. SysTick Control and Status Register
4.4.2. SysTick Reload Value Register
4.4.3. SysTick Current Value Register
4.4.4. SysTick Calibration Value Register
4.4.5. SysTick design hints and tips
4.5. Processor features
4.5.1. Cache Level ID Register
4.5.2. Cache Type Register
4.5.3. Cache Size ID Register
4.5.4. Cache Size Selection Register
4.5.5. Instruction Error bank Register 0-1
4.5.6. Data Error bank Register 0-1
4.6. Optional Memory Protection Unit
4.6.1. MPU Type Register
4.6.2. MPU Control Register
4.6.3. MPU Region Number Register
4.6.4. MPU Region Base Address Register
4.6.5. MPU Region Attribute and Size Register
4.6.6. MPU access permission attributes
4.6.7. MPU mismatch
4.6.8. Updating an MPU region
4.6.9. MPU design hints and tips
4.7. Floating Point Unit
4.7.1. Coprocessor Access Control Register
4.7.2. Floating-point Context Control Register
4.7.3. Floating-point Context Address Register
4.7.4. Floating-point Status Control Register
4.7.5. Floating-point Default Status Control Register
4.7.6. Enabling the FPU
4.8. Cache maintenance operations
4.8.1. Full instruction cache operation
4.8.2. Instruction and data cache operations by address
4.8.3. Data cache operations by set-way
4.8.4. Accessing the Cortex-M7 NVIC cache maintenance operations using CMSIS
4.8.5. Initializing and enabling the L1 cache
4.8.6. Faults handling considerations
4.8.7. Cache maintenance design hints and tips
4.9. Access control
4.9.1. Instruction and Data Tightly-Coupled Memory Control Registers
4.9.2. AHBP Control Register
4.9.3. L1 Cache Control Register
4.9.4. AHB Slave Control Register
4.9.5. Auxiliary Bus Fault Status register
A. Cortex-M7 Options
A.1. Cortex-M7 processor options
B. Revisions

List of Tables

1. Typographical conventions
2.1. Summary of processor mode, execution privilege level, and stack use options
2.2. Core register set summary
2.3. PSR register combinations
2.4. APSR bit assignments
2.5. IPSR bit assignments
2.6. EPSR bit assignments
2.7. PRIMASK register bit assignments
2.8. FAULTMASK register bit assignments
2.9. BASEPRI register bit assignments
2.10. CONTROL register bit assignments
2.11. Memory access behavior
2.12. Memory region shareability and cache policies
2.13. CMSIS functions for exclusive access instructions
2.14. Properties of the different exception types
2.15. Exception return behavior
2.16. Faults
2.17. Fault status and fault address registers
3.1. Cortex-M7 instructions
3.2. CMSIS functions to generate some Cortex-M7 processor instructions
3.3. CMSIS functions to access the special registers
3.4. Condition code suffixes
3.5. Memory access instructions
3.6. Offset ranges
3.7. Offset ranges
3.8. Data processing instructions
3.9. Multiply and divide instructions
3.10. Saturating instructions
3.11. Packing and unpacking instructions
3.12. Bit field instructions
3.13. Branch and control instructions
3.14. Branch ranges
3.15. Floating-point instructions
3.16. Miscellaneous instructions
4.1. Core peripheral register regions
4.2. NVIC register summary
4.3. CMSIS access NVIC functions
4.4. ISER bit assignments
4.5. ICER bit assignments
4.6. ISPR bit assignments
4.7. ICPR bit assignments
4.8. IABR bit assignments
4.9. IPR bit assignments
4.10. STIR bit assignments
4.11. CMSIS functions for NVIC control
4.12. Summary of the system control block registers
4.13. ACTLR bit assignments
4.14. CPUID bit assignments
4.15. ICSR bit assignments
4.16. VTOR bit assignments
4.17. AIRCR bit assignments
4.18. Priority grouping
4.19. SCR bit assignments
4.20. CCR bit assignments
4.21. System fault handler priority fields
4.22. SHPR1 register bit assignments
4.23. SHPR2 register bit assignments
4.24. SHPR3 register bit assignments
4.25. SHCSR bit assignments
4.26. MMFSR bit assignments
4.27. BFSR bit assignments
4.28. UFSR bit assignments
4.29. HFSR bit assignments
4.30. MMFAR bit assignments
4.31. BFAR bit assignments
4.32. CMSIS function for system control
4.33. System timer registers summary
4.34. SysTick SYST_CSR bit assignments
4.35. SYST_RVR bit assignments
4.36. SYST_CVR bit assignments
4.37. SYST_CALIB bit assignments
4.38. CMSIS functions for SysTick control
4.39. Identification space summary
4.40. CLIDR bit assignments
4.41. CTR bit assignments
4.42. CCSIDR bit assignments
4.43. CCSIDR encodings
4.44. CSSELR bit assignments
4.45. IEBR0-1 bit assignments
4.46. DEBR0-1 bit assignments
4.47. Memory attributes summary
4.48. MPU registers summary
4.49. TYPE bit assignments
4.50. MPU_CTRL bit assignments
4.51. MPU_RNR bit assignments
4.52. MPU_RBAR bit assignments
4.53. MPU_RASR bit assignments
4.54. Example SIZE field values
4.55. TEX, C, B, and S encoding
4.56. Cache policy for memory attribute encoding
4.57. AP encoding
4.58. Cortex-M7 floating-point system registers
4.59. CPACR bit assignments
4.60. FPCCR bit assignments
4.61. FPCAR bit assignments
4.62. FPSCR bit assignments
4.63. FPDSCR bit assignments
4.64. Cache Maintenance Space register summary
4.65. Cache operations registers bit assignments
4.66. Cache operations by set-way bit assignments
4.67. CMSIS access cache maintenance operations
4.68. Access control register summary
4.69. ITCMCR and DTCMCR bit assignments
4.70. AHBPCR bit assignments
4.71. CACR bit assignments
4.72. AHBSCR bit assignments
4.73. ABFSR bit assignments
A.1. Effects of the Cortex-M7 processor implementation options
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C

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Revision History
Revision A19 March 2015First release for r1p0
Revision B07 July 2015First release for r1p1
Revision C15 November 2018First release for r1p2
Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C