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2.3.2. Exception types

The exception types are:

Reset

Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode.

NMI

A Non-Maskable Interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:

  • masked or prevented from activation by any other exception

  • preempted by any exception other than Reset.

HardFault

A HardFault is an exception that occurs because of an error. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.

SVCall

A Supervisor Call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.

PendSV

PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active.

SysTick

If the device implements the SysTick timer, a SysTick exception is generated when the SysTick timer reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick.

Interrupt (IRQ)

An interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.

Table 2.11. Properties of the different exception types

Exception number [a]

IRQ number [a]Exception typePriorityVector address [b]Activation
1-Reset

-3, the highest

0x00000004Asynchronous
2-14NMI-20x00000008Asynchronous
3-13HardFault-10x0000000CSynchronous
4-10-Reserved---
11-5SVCall

Configurable [e]

0x0000002CSynchronous
12-13-Reserved---
14-2PendSV

Configurable [e]

0x00000038Asynchronous
15-1

SysTick[c]

Configurable [e]

0x0000003C Asynchronous
15-

Reserved

---
16 and above[d]0 and above

Interrupt (IRQ)

Configurable [e]

0x00000040 and above [f]Asynchronous

[a] To simplify the software layer, CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register.

[b] See Vector table for more information.

[c] If your device does not implement the SysTick timer, exception number 15 is reserved.

[d] The number of IRQ interrupts is implementation-defined, in the range 0-32. Unimplemented IRQ exception numbersare reserved, for example if the device implements only one IRQ, exception numbers 17 and above are reserved.

[e] See Interrupt Priority Registers.

[f] Increasing in steps of 4.


For an asynchronous exception, other than reset, the processor can execute additional instructions between when the exception is triggered and when the processor enters the exception handler.

Privileged software can disable the exceptions that Table 2.11 shows as having configurable priority, see Interrupt Clear-Enable Register.

For more information about HardFaults, see Fault handling.

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