Cortex-M0+ Devices Generic User Guide: 4.5.6. MPU access permission attributes

4.5.6. MPU access permission attributes

This section describes the MPU access permission attributes. The access permission bits, C, B, S, AP, and XN, of the MPU_RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.

Table 4.32 shows the encodings for the C, B, and S access permission bits.

Table 4.32. C, B, and S encoding

C	B	S	Memory type	Shareability	Other attributes
0	0	x^[a]	Strongly-ordered	Shareable	-
0	1	x^[a]	Device	Shareable	-
1	0	0	Normal	Not shareable	Outer and inner write-through. No write allocate.
	0	1	Normal	Shareable	Outer and inner write-through. No write allocate.
	1	0	Normal	Not shareable	Outer and inner write-back. No write allocate.
	1	1	Normal	Shareable	Outer and inner write-back. No write allocate.
^[a]The MPU ignores the value of this bit.

Table 4.33 shows the AP encodings that define the access permissions for privileged and unprivileged software.

Table 4.33. AP encoding

AP[2:0]	Privileged permissions	Unprivileged permissions	Description
000	No access	No access	All accesses generate a permission fault
001	RW	No access	Access from privileged software only
010	RW	RO	Writes by unprivileged software generate a permission fault
011	RW	RW	Full access
100	Unpredictable	Unpredictable	Reserved
101	RO	No access	Reads by privileged software only
110	RO	RO	Read only, by privileged or unprivileged software
111	RO	RO	Read only, by privileged or unprivileged software

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