Cortex-M0+ Devices Generic User Guide
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4.4.1. SysTick Control and Status Register

The SYST_CSR enables the SysTick features. See the register summary in Table 4.19 for its attributes. The bit assignments are:

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Table 4.20. SYST_CSR bit assignments

BitsNameFunction
[31:17]-Reserved
[16]COUNTFLAG

Returns 1 if timer counted to 0 since the last read of this register

[15:3]-Reserved
[2]CLKSOURCE

Selects the SysTick timer clock source:

0 = external reference clock

1 = processor clock.

[1]TICKINT

Enables SysTick exception request:

0 = counting down to zero does not assert the SysTick exception request

1 = counting down to zero asserts the SysTick exception request.

[0]ENABLE

Enables the counter:

0 = counter disabled

1 = counter enabled.


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