| Copyright © 2012 ARM. All rights reserved. | ARM DUI 0662A |
| Non-Confidential | ID041812 |
 PDF version | |
| Home > The Cortex-M0+ Processor > Power management |
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The Cortex-M0+ processor sleep modes reduce power consumption:
a sleep mode, that stops the processor clock
a deep sleep mode, that stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see System Control Register .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.
| Copyright © 2012 ARM. All rights reserved. | ARM DUI 0662A |
| Non-Confidential | ID041812 |
| PDF version | |
| Home > The Cortex-M0+ Processor > Power management |