Cortex-M0+ Devices Generic User Guide: 4.1. About the Cortex-M0+ peripherals

Cortex-M0+ Devices Generic User Guide

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4.1. About the Cortex-M0+ peripherals

The address map of the Private Peripheral Bus (PPB) is:

Table 4.1. Core peripheral register regions

Address	Core peripheral	Description
`0xE000E008`-`0xE000E00F`	System Control Block	Table 4.9
`0xE000E010`-`0xE000E01F`	Reserved	-
`0xE000E010`-`0xE000E01F`	SysTick^[a]	Table 4.19
`0xE000E100`-`0xE000E4EF`	Nested Vectored Interrupt Controller	Table 4.2
`0xE000ED00`-`0xE000ED3F`	System Control Block	Table 4.9
`0xE000ED90`	MPU Type Register	RAZ Indicates no MPU is implemented ^[b] non-zero Table 4.25
`0xE000ED94`-`0xE000EDB8`	Memory Protection Unit^[c]	Table 4.25
`0xE000EF00`-`0xE000EF03`	Nested Vectored Interrupt Controller	Table 4.2
^[a]The system timer is an optional peripheral. ^[b]Software can read the MPU Type Register at `0xE000ED90` to test for the presence of a Memory Protection Unit (MPU). ^[c]The Memory Protection Unit is an optional peripheral.

In register descriptions:

the register type is described as follows:
RW
Read and write.
RO
Read-only.
WO
Write-only.
the required privilege applies only to some optional peripherals. It gives the privilege level required to access the register, as follows:
Privileged
Only privileged software can access the register.
Unprivileged
Both unprivileged and privileged software can access the register.

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