10.4.5 Constraint codes for AArch64 state

The following constraint codes are specific to AArch64 state.

Registers

r

The compiler can use a 64-bit general purpose register, X0-X30.

If you want the compiler to use the 32-bit general purpose registers W0-W31 instead, use the w template modifier.

w

The compiler can use a SIMD or floating-point register, V0-V31.

The b, h, s, d, and q template modifiers can override this behavior.

x

Operand must be a 128-bit vector type.

The compiler can use a low SIMD register, V0-V15.

Constants

z
A constant with value zero, printed as the zero register (XZR or WZR). Useful when combined with r (see 10.4.6 Using multiple alternative operand constraints) to represent an operand that can be either a general-purpose register or the zero register.
I
[0, 4095], with an optional left shift by 12. The range that the ADD and SUB instructions accept.
J
[-4095, 0], with an optional left shift by 12.
K
An immediate that is valid for 32-bit logical instructions. For example, AND, ORR, EOR.
L
An immediate that is valid for 64-bit logical instructions. For example, AND, ORR, EOR.
M
An immediate that is valid for a MOV instruction with a destination of a 32-bit register. Valid values are all values that the K constraint accepts, plus the values that the MOVZ, MOVN, and MOVK instructions accept.
N
An immediate that is valid for a MOV instruction with a destination of a 64-bit register. Valid values are all values that the L constraint accepts, plus the values that the MOVZ, MOVN, and MOVK instructions accept.
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