ARM® Compiler armasm User Guide

Version 6.00


List of Topics

Conventions and Feedback
Overview of armasm
About the ARM Compiler toolchain assemblers
Key features of the assembler
How the assembler works
Directives that can be omitted in pass 2 of the assembler
Overview of the ARM Architecture
About the ARM architecture
A64, A32, and T32 instruction sets
Changing between AArch64 and AArch32 states
Advanced SIMD
Floating-point hardware
Overview of AArch32 state
Changing between A32 and T32 state
Processor modes, and privileged and unprivileged software execution
Registers in AArch32 state
General-purpose registers in AArch32 state
Register accesses in AArch32 state
Predeclared core register names in AArch32 state
Predeclared extension register names in AArch32 state
Program Counter in AArch32 state
Application Program Status Register
The Q flag in AArch32 state
Current Program Status Register in AArch32
Saved Program Status Registers (SPSRs) in AArch32 state
A32 instruction set overview
Media processing instructions
Access to the inline barrel shifter in AArch32 state
Overview of AArch64 state
Registers in AArch64 state
Exception levels
Link registers
Stack Pointer register
Predeclared core register names in AArch64 state
Predeclared extension register names in AArch64 state
Program Counter in AArch64 state
Conditional execution in AArch64 state
The Q flag in AArch64 state
Process State
Saved Program Status Registers (SPSRs) in AArch64 state
A64 instruction set overview
Structure of Assembly Language Modules
Syntax of source lines in assembly language
Literals
ELF sections and the AREA directive
An example assembly language module
Writing A32/T32 Assembly Language
Unified Assembler Language
Syntax differences between UAL and A64 assembly language
Subroutine calls
Load immediates into registers
Load immediate values using MOV and MVN
Load 32-bit values to a register using MOV32
Load immediate 32-bit values to a register using LDR Rd, =const
Literal pools
Load addresses into registers
Load addresses to a register using ADR
Load addresses to a register using ADRL
Load addresses to a register using LDR Rd, =label
Other ways to load and store registers
Load and store multiple register instructions
A32 and T32 load and store multiple instructions
Stack implementation using LDM and STM
Stack operations for nested subroutines
Block copy with LDM and STM
Memory accesses
Read-Modify-Write procedure
Optional hash
Use of macros
Test-and-branch macro example
Unsigned integer division macro example
Instruction and directive relocations
Symbol versions
Frame directives
Exception tables and Unwind tables
Condition Codes
Conditional instructions
Conditional execution in A32 code
Conditional execution in T32 code
Conditional execution in A64 code
Condition flags
Updates to the condition flags in A32/T32 code
Updates to the condition flags in A64 code
Floating-point instructions that update the condition flags
Carry flag
Overflow flag
Condition code suffixes
Comparison of condition code meanings in integer and floating-point code
Benefits of using conditional execution in A32 and T32 code
Illustration of the benefits of conditional instructions in A32 and T32 code
Optimization for execution speed
Using armasm
armasm command-line syntax
armasm commands listed in groups
Specify command-line options with an environment variable
Using stdin to input source code to armasm
Built-in variables and constants
Versions of armasm
Diagnostic messages
Interlocks diagnostics
Automatic IT block generation in T32 code
T32 branch target alignment
T32 code size diagnostics
A32 and T32 instruction portability diagnostics
T32 instruction width
Two pass assembler diagnostics
Address alignment in A32/T32 code
Address alignment in A64 code
Instruction width selection in T32 code
Symbols, Literals, Expressions, and Operators
Symbol naming rules
Variables
Numeric constants
Assembly time substitution of variables
Register-relative and PC-relative expressions
Labels
Labels for PC-relative addresses
Labels for register-relative addresses
Labels for absolute addresses
Numeric local labels
Syntax of numeric local labels
String expressions
String literals
Numeric expressions
Numeric literals
Floating-point literals
Logical expressions
Logical literals
Unary operators
Binary operators
Multiplicative operators
String manipulation operators
Shift operators
Addition, subtraction, and logical operators
Relational operators
Boolean operators
Operator precedence
Difference between operator precedence in assembly language and C
Advanced SIMD and Floating-point Programming
Architecture support for Advanced SIMD and floating-point
Extension register bank mapping in AArch32 state
Extension register bank mapping in AArch64 state
Views of the Advanced SIMD register bank in AArch32 state
Views of the Advanced SIMD register bank in AArch64 state
Views of the floating-point extension register bank in AArch32 state
Views of the floating-point extension register bank in AArch64 state
Differences between A32/T32 and A64 Advanced SIMD and floating-point instruction syntax
Load values to SIMD and floating-point registers
Conditional execution of T32 Advanced SIMD and floating-point instructions
Floating-point exceptions in A32/T32 instructions
Advanced SIMD and floating-point data types in A32/T32 instructions
Advanced SIMD vectors
Normal Advanced SIMD instructions
Long Advanced SIMD instructions
Wide Advanced SIMD instructions
Narrow Advanced SIMD instructions
Saturating Advanced SIMD instructions
Advanced SIMD scalars
Extended notation in A32/T32 code
Polynomial arithmetic over {0,1}
Advanced SIMD and floating-point system registers in AArch32 state
Flush-to-zero mode
When to use flush-to-zero mode
The effects of using flush-to-zero mode
Operations not affected by flush-to-zero mode

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A14 March 2014ARM Compiler v6.00 Release
Copyright © 2014 ARM. All rights reserved.ARM DUI 0801A
Non-ConfidentialID031214