ARM® Compiler armasm User Guide

Version 6.4


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Overview of the Assembler
1.1 About the ARM Compiler toolchain assemblers
1.2 Key features of the assembler
1.3 How the assembler works
1.4 Directives that can be omitted in pass 2 of the assembler
1.5 Support level definitions
2 Overview of the ARM Architecture
2.1 About the ARM architecture
2.2 A32 and T32 instruction sets
2.3 A64 instruction set
2.4 Changing between AArch64 and AArch32 states
2.5 Advanced SIMD
2.6 Floating-point hardware
3 Overview of AArch32 state
3.1 Changing between A32 and T32 instruction set states
3.2 Processor modes, and privileged and unprivileged software execution
3.3 Processor modes in ARMv6-M, ARMv7-M, and ARMv8-M
3.4 Registers in AArch32 state
3.5 General-purpose registers in AArch32 state
3.6 Register accesses in AArch32 state
3.7 Predeclared core register names in AArch32 state
3.8 Predeclared extension register names in AArch32 state
3.9 Program Counter in AArch32 state
3.10 The Q flag in AArch32 state
3.11 Application Program Status Register
3.12 Current Program Status Register in AArch32
3.13 Saved Program Status Registers in AArch32 state
3.14 A32 and T32 instruction set overview
3.15 Access to the inline barrel shifter in AArch32 state
4 Overview of AArch64 state
4.1 Registers in AArch64 state
4.2 Exception levels
4.3 Link registers
4.4 Stack Pointer register
4.5 Predeclared core register names in AArch64 state
4.6 Predeclared extension register names in AArch64 state
4.7 Program Counter in AArch64 state
4.8 Conditional execution in AArch64 state
4.9 The Q flag in AArch64 state
4.10 Process State
4.11 Saved Program Status Registers in AArch64 state
4.12 A64 instruction set overview
5 Structure of Assembly Language Modules
5.1 Syntax of source lines in assembly language
5.2 Literals
5.3 ELF sections and the AREA directive
5.4 An example A32 assembly language module
6 Writing A32/T32 Assembly Language
6.1 About the Unified Assembler Language
6.2 Syntax differences between UAL and A64 assembly language
6.3 Register usage in subroutine calls
6.4 Load immediate values
6.5 Load immediate values using MOV and MVN
6.6 Load immediate values using MOV32
6.7 Load immediate values using LDR Rd, =const
6.8 Literal pools
6.9 Load addresses into registers
6.10 Load addresses to a register using ADR
6.11 Load addresses to a register using ADRL
6.12 Load addresses to a register using LDR Rd, =label
6.13 Other ways to load and store registers
6.14 Load and store multiple register instructions
6.15 Load and store multiple register instructions in A32 and T32
6.16 Stack implementation using LDM and STM
6.17 Stack operations for nested subroutines
6.18 Block copy with LDM and STM
6.19 Memory accesses
6.20 The Read-Modify-Write operation
6.21 Optional hash with immediate constants
6.22 Use of macros
6.23 Test-and-branch macro example
6.24 Unsigned integer division macro example
6.25 Instruction and directive relocations
6.26 Symbol versions
6.27 Frame directives
6.28 Exception tables and Unwind tables
7 Condition Codes
7.1 Conditional instructions
7.2 Conditional execution in A32 code
7.3 Conditional execution in T32 code
7.4 Conditional execution in A64 code
7.5 Condition flags
7.6 Updates to the condition flags in A32/T32 code
7.7 Updates to the condition flags in A64 code
7.8 Floating-point instructions that update the condition flags
7.9 Carry flag
7.10 Overflow flag
7.11 Condition code suffixes
7.12 Condition code suffixes and related flags
7.13 Comparison of condition code meanings in integer and floating-point code
7.14 Benefits of using conditional execution in A32 and T32 code
7.15 Example showing the benefits of conditional instructions in A32 and T32 code
7.16 Optimization for execution speed
8 Using armasm
8.1 armasm command-line syntax
8.2 Specify command-line options with an environment variable
8.3 Using stdin to input source code to the assembler
8.4 Built-in variables and constants
8.5 Identifying versions of armasm in source code
8.6 Diagnostic messages
8.7 Interlocks diagnostics
8.8 Automatic IT block generation in T32 code
8.9 T32 branch target alignment
8.10 T32 code size diagnostics
8.11 A32 and T32 instruction portability diagnostics
8.12 T32 instruction width diagnostics
8.13 Two pass assembler diagnostics
8.14 Using the C preprocessor
8.15 Address alignment in A32/T32 code
8.16 Address alignment in A64 code
8.17 Instruction width selection in T32 code
9 Advanced SIMD Programming
9.1 Architecture support for Advanced SIMD
9.2 Extension register bank mapping for Advanced SIMD in AArch32 state
9.3 Extension register bank mapping for Advanced SIMD in AArch64 state
9.4 Views of the Advanced SIMD register bank in AArch32 state
9.5 Views of the Advanced SIMD register bank in AArch64 state
9.6 Differences between A32/T32 and A64 Advanced SIMD instruction syntax
9.7 Load values to Advanced SIMD registers
9.8 Conditional execution of A32/T32 Advanced SIMD instructions
9.9 Floating-point exceptions for Advanced SIMD in A32/T32 instructions
9.10 Advanced SIMD data types in A32/T32 instructions
9.11 Polynomial arithmetic over {0,1}
9.12 Advanced SIMD vectors
9.13 Normal, long, wide, and narrow Advanced SIMD instructions
9.14 Saturating Advanced SIMD instructions
9.15 Advanced SIMD scalars
9.16 Extended notation extension for Advanced SIMD in A32/T32 code
9.17 Advanced SIMD system registers in AArch32 state
9.18 Flush-to-zero mode in Advanced SIMD
9.19 When to use flush-to-zero mode in Advanced SIMD
9.20 The effects of using flush-to-zero mode in Advanced SIMD
9.21 Advanced SIMD operations not affected by flush-to-zero mode
10 Floating-point Programming
10.1 Architecture support for floating-point
10.2 Extension register bank mapping for floating-point in AArch32 state
10.3 Extension register bank mapping in AArch64 state
10.4 Views of the floating-point extension register bank in AArch32 state
10.5 Views of the floating-point extension register bank in AArch64 state
10.6 Differences between A32/T32 and A64 floating-point instruction syntax
10.7 Load values to floating-point registers
10.8 Conditional execution of A32/T32 floating-point instructions
10.9 Floating-point exceptions for floating-point in A32/T32 instructions
10.10 Floating-point data types in A32/T32 instructions
10.11 Extended notation extension for floating-point in A32/T32 code
10.12 Floating-point system registers in AArch32 state
10.13 Flush-to-zero mode in floating-point
10.14 When to use flush-to-zero mode in floating-point
10.15 The effects of using flush-to-zero mode in floating-point
10.16 Floating-point operations not affected by flush-to-zero mode
11 armasm Command-line Options
11.1 --16
11.2 --32
11.3 --apcs=qualifier…qualifier
11.4 --arm
11.5 --arm_only
11.6 --bi
11.7 --bigend
11.8 --brief_diagnostics, --no_brief_diagnostics
11.9 --checkreglist
11.10 --cpreproc
11.11 --cpreproc_opts=option[,option,…]
11.12 --cpu=list
11.13 --cpu=name
11.14 --debug
11.15 --depend=dependfile
11.16 --depend_format=string
11.17 --diag_error=tag[,tag,…]
11.18 --diag_remark=tag[,tag,…]
11.19 --diag_style={arm|ide|gnu}
11.20 --diag_suppress=tag[,tag,…]
11.21 --diag_warning=tag[,tag,…]
11.22 --dllexport_all
11.23 --dwarf2
11.24 --dwarf3
11.25 --errors=errorfile
11.26 --exceptions, --no_exceptions
11.27 --exceptions_unwind, --no_exceptions_unwind
11.28 --execstack, --no_execstack
11.29 --execute_only
11.30 --fpmode=model
11.31 --fpu=list
11.32 --fpu=name
11.33 -g
11.34 --help
11.35 -idir[,dir, …]
11.36 --keep
11.37 --length=n
11.38 --li
11.39 --library_type=lib
11.40 --list=file
11.41 --list=
11.42 --littleend
11.43 -m
11.44 --maxcache=n
11.45 --md
11.46 --no_code_gen
11.47 --no_esc
11.48 --no_hide_all
11.49 --no_regs
11.50 --no_terse
11.51 --no_warn
11.52 -o filename
11.53 --pd
11.54 --predefine "directive"
11.55 --reduce_paths, --no_reduce_paths
11.56 --regnames
11.57 --report-if-not-wysiwyg
11.58 --show_cmdline
11.59 --thumb
11.60 --unaligned_access, --no_unaligned_access
11.61 --unsafe
11.62 --untyped_local_labels
11.63 --version_number
11.64 --via=filename
11.65 --vsn
11.66 --width=n
11.67 --xref
12 Symbols, Literals, Expressions, and Operators
12.1 Symbol naming rules
12.2 Variables
12.3 Numeric constants
12.4 Assembly time substitution of variables
12.5 Register-relative and PC-relative expressions
12.6 Labels
12.7 Labels for PC-relative addresses
12.8 Labels for register-relative addresses
12.9 Labels for absolute addresses
12.10 Numeric local labels
12.11 Syntax of numeric local labels
12.12 String expressions
12.13 String literals
12.14 Numeric expressions
12.15 Syntax of numeric literals
12.16 Syntax of floating-point literals
12.17 Logical expressions
12.18 Logical literals
12.19 Unary operators
12.20 Binary operators
12.21 Multiplicative operators
12.22 String manipulation operators
12.23 Shift operators
12.24 Addition, subtraction, and logical operators
12.25 Relational operators
12.26 Boolean operators
12.27 Operator precedence
12.28 Difference between operator precedence in assembly language and C
13 A32 and T32 Instructions
13.1 A32 and T32 instruction summary
13.2 Instruction width specifiers
13.3 Flexible second operand (Operand2)
13.4 Syntax of Operand2 as a constant
13.5 Syntax of Operand2 as a register with optional shift
13.6 Shift operations
13.7 Saturating instructions
13.8 ADC
13.9 ADD
13.10 ADR (PC-relative)
13.11 ADR (register-relative)
13.12 ADRL pseudo-instruction
13.13 AND
13.14 ASR
13.15 B
13.16 BFC
13.17 BFI
13.18 BIC
13.19 BKPT
13.20 BL
13.21 BLX, BLXNS
13.22 BX, BXNS
13.23 BXJ
13.24 CBZ and CBNZ
13.25 CDP and CDP2
13.26 CLREX
13.27 CLZ
13.28 CMP and CMN
13.29 CPS
13.30 CPY pseudo-instruction
13.31 DBG
13.32 DCPS1 (T32 instruction)
13.33 DCPS2 (T32 instruction)
13.34 DCPS3 (T32 instruction)
13.35 DMB
13.36 DSB
13.37 EOR
13.38 ERET
13.39 HLT
13.40 HVC
13.41 ISB
13.42 IT
13.43 LDA
13.44 LDAEX
13.45 LDC and LDC2
13.46 LDM
13.47 LDR (immediate offset)
13.48 LDR (PC-relative)
13.49 LDR (register offset)
13.50 LDR (register-relative)
13.51 LDR pseudo-instruction
13.52 LDR, unprivileged
13.53 LDREX
13.54 LSL
13.55 LSR
13.56 MCR and MCR2
13.57 MCRR and MCRR2
13.58 MLA
13.59 MLS
13.60 MOV
13.61 MOV32 pseudo-instruction
13.62 MOVT
13.63 MRC and MRC2
13.64 MRRC and MRRC2
13.65 MRS (PSR to general-purpose register)
13.66 MRS (system coprocessor register to ARM register)
13.67 MSR (ARM register to system coprocessor register)
13.68 MSR (general-purpose register to PSR)
13.69 MUL
13.70 MVN
13.71 NEG pseudo-instruction
13.72 NOP
13.73 ORN (T32 only)
13.74 ORR
13.75 PKHBT and PKHTB
13.76 PLD, PLDW, and PLI
13.77 POP
13.78 PUSH
13.79 QADD
13.80 QADD8
13.81 QADD16
13.82 QASX
13.83 QDADD
13.84 QDSUB
13.85 QSAX
13.86 QSUB
13.87 QSUB8
13.88 QSUB16
13.89 RBIT
13.90 REV
13.91 REV16
13.92 REVSH
13.93 RFE
13.94 ROR
13.95 RRX
13.96 RSB
13.97 RSC
13.98 SADD8
13.99 SADD16
13.100 SASX
13.101 SBC
13.102 SBFX
13.103 SDIV
13.104 SEL
13.105 SETEND
13.106 SEV
13.107 SEVL
13.108 SG
13.109 SHADD8
13.110 SHADD16
13.111 SHASX
13.112 SHSAX
13.113 SHSUB8
13.114 SHSUB16
13.115 SMC
13.116 SMLAxy
13.117 SMLAD
13.118 SMLAL
13.119 SMLALD
13.120 SMLALxy
13.121 SMLAWy
13.122 SMLSD
13.123 SMLSLD
13.124 SMMLA
13.125 SMMLS
13.126 SMMUL
13.127 SMUAD
13.128 SMULxy
13.129 SMULL
13.130 SMULWy
13.131 SMUSD
13.132 SRS
13.133 SSAT
13.134 SSAT16
13.135 SSAX
13.136 SSUB8
13.137 SSUB16
13.138 STC and STC2
13.139 STL
13.140 STLEX
13.141 STM
13.142 STR (immediate offset)
13.143 STR (register offset)
13.144 STR, unprivileged
13.145 STREX
13.146 SUB
13.147 SUBS pc, lr
13.148 SVC
13.149 SWP and SWPB
13.150 SXTAB
13.151 SXTAB16
13.152 SXTAH
13.153 SXTB
13.154 SXTB16
13.155 SXTH
13.156 SYS
13.157 TBB and TBH
13.158 TEQ
13.159 TST
13.160 TT, TTT, TTA, TTAT
13.161 UADD8
13.162 UADD16
13.163 UASX
13.164 UBFX
13.165 UDIV
13.166 UHADD8
13.167 UHADD16
13.168 UHASX
13.169 UHSAX
13.170 UHSUB8
13.171 UHSUB16
13.172 UMAAL
13.173 UMLAL
13.174 UMULL
13.175 UND pseudo-instruction
13.176 UQADD8
13.177 UQADD16
13.178 UQASX
13.179 UQSAX
13.180 UQSUB8
13.181 UQSUB16
13.182 USAD8
13.183 USADA8
13.184 USAT
13.185 USAT16
13.186 USAX
13.187 USUB8
13.188 USUB16
13.189 UXTAB
13.190 UXTAB16
13.191 UXTAH
13.192 UXTB
13.193 UXTB16
13.194 UXTH
13.195 WFE
13.196 WFI
13.197 YIELD
14 Advanced SIMD Instructions (32-bit)
14.1 Summary of Advanced SIMD instructions
14.2 Summary of shared Advanced SIMD and floating-point instructions
14.3 Cryptographic instructions
14.4 Interleaving provided by load and store element and structure instructions
14.5 Alignment restrictions in load and store element and structure instructions
14.6 VABA and VABAL
14.7 VABD and VABDL
14.8 VABS
14.9 VACLE, VACLT, VACGE and VACGT
14.10 VADD
14.11 VADDHN
14.12 VADDL and VADDW
14.13 VAND (immediate)
14.14 VAND (register)
14.15 VBIC (immediate)
14.16 VBIC (register)
14.17 VBIF
14.18 VBIT
14.19 VBSL
14.20 VCEQ (immediate #0)
14.21 VCEQ (register)
14.22 VCGE (immediate #0)
14.23 VCGE (register)
14.24 VCGT (immediate #0)
14.25 VCGT (register)
14.26 VCLE (immediate #0)
14.27 VCLS
14.28 VCLE (register)
14.29 VCLT (immediate #0)
14.30 VCLT (register)
14.31 VCLZ
14.32 VCNT
14.33 VCVT (between fixed-point or integer, and floating-point)
14.34 VCVT (between half-precision and single-precision floating-point)
14.35 VCVT (from floating-point to integer with directed rounding modes)
14.36 VCVTB, VCVTT (between half-precision and double-precision)
14.37 VDUP
14.38 VEOR
14.39 VEXT
14.40 VFMA, VFMS
14.41 VHADD
14.42 VHSUB
14.43 VLDn (single n-element structure to one lane)
14.44 VLDn (single n-element structure to all lanes)
14.45 VLDn (multiple n-element structures)
14.46 VLDM
14.47 VLDR
14.48 VLDR (post-increment and pre-decrement)
14.49 VLDR pseudo-instruction
14.50 VMAX and VMIN
14.51 VMAXNM, VMINNM
14.52 VMLA
14.53 VMLA (by scalar)
14.54 VMLAL (by scalar)
14.55 VMLAL
14.56 VMLS (by scalar)
14.57 VMLS
14.58 VMLSL
14.59 VMLSL (by scalar)
14.60 VMOV (immediate)
14.61 VMOV (register)
14.62 VMOV (between two ARM registers and a 64-bit extension register)
14.63 VMOV (between an ARM register and an Advanced SIMD scalar)
14.64 VMOVL
14.65 VMOVN
14.66 VMOV2
14.67 VMRS
14.68 VMSR
14.69 VMUL
14.70 VMUL (by scalar)
14.71 VMULL
14.72 VMULL (by scalar)
14.73 VMVN (register)
14.74 VMVN (immediate)
14.75 VNEG
14.76 VORN (register)
14.77 VORN (immediate)
14.78 VORR (register)
14.79 VORR (immediate)
14.80 VPADAL
14.81 VPADD
14.82 VPADDL
14.83 VPMAX and VPMIN
14.84 VPOP
14.85 VPUSH
14.86 VQABS
14.87 VQADD
14.88 VQDMLAL and VQDMLSL (by vector or by scalar)
14.89 VQDMULH (by vector or by scalar)
14.90 VQDMULL (by vector or by scalar)
14.91 VQMOVN and VQMOVUN
14.92 VQNEG
14.93 VQRDMULH (by vector or by scalar)
14.94 VQRSHL (by signed variable)
14.95 VQRSHRN and VQRSHRUN (by immediate)
14.96 VQSHL (by signed variable)
14.97 VQSHL and VQSHLU (by immediate)
14.98 VQSHRN and VQSHRUN (by immediate)
14.99 VQSUB
14.100 VRADDHN
14.101 VRECPE
14.102 VRECPS
14.103 VREV16, VREV32, and VREV64
14.104 VRHADD
14.105 VRSHL (by signed variable)
14.106 VRSHR (by immediate)
14.107 VRSHRN (by immediate)
14.108 VRINT
14.109 VRSQRTE
14.110 VRSQRTS
14.111 VRSRA (by immediate)
14.112 VRSUBHN
14.113 VSHL (by immediate)
14.114 VSHL (by signed variable)
14.115 VSHLL (by immediate)
14.116 VSHR (by immediate)
14.117 VSHRN (by immediate)
14.118 VSLI
14.119 VSRA (by immediate)
14.120 VSRI
14.121 VSTM
14.122 VSTn (multiple n-element structures)
14.123 VSTn (single n-element structure to one lane)
14.124 VSTR
14.125 VSTR (post-increment and pre-decrement)
14.126 VSUB
14.127 VSUBHN
14.128 VSUBL and VSUBW
14.129 VSWP
14.130 VTBL and VTBX
14.131 VTRN
14.132 VTST
14.133 VUZP
14.134 VZIP
15 Floating-point Instructions (32-bit)
15.1 Summary of floating-point instructions
15.2 VABS (floating-point)
15.3 VADD (floating-point)
15.4 VCMP, VCMPE
15.5 VCVT (between single-precision and double-precision)
15.6 VCVT (between floating-point and integer)
15.7 VCVT (from floating-point to integer with directed rounding modes)
15.8 VCVT (between floating-point and fixed-point)
15.9 VCVTB, VCVTT (half-precision extension)
15.10 VCVTB, VCVTT (between half-precision and double-precision)
15.11 VDIV
15.12 VFMA, VFMS, VFNMA, VFNMS (floating-point)
15.13 VLDM (floating-point)
15.14 VLDR (floating-point)
15.15 VLDR (post-increment and pre-decrement, floating-point)
15.16 VLDR pseudo-instruction (floating-point)
15.17 VMAXNM, VMINNM (floating-point)
15.18 VMLA (floating-point)
15.19 VMLS (floating-point)
15.20 VMOV (floating-point)
15.21 VMOV (between one ARM register and single precision floating-point register)
15.22 VMOV (between two ARM registers and one or two extension registers)
15.23 VMOV (between an ARM register and half a double precision floating-point register)
15.24 VMRS (floating-point)
15.25 VMSR (floating-point)
15.26 VMUL (floating-point)
15.27 VNEG (floating-point)
15.28 VNMLA (floating-point)
15.29 VNMLS (floating-point)
15.30 VNMUL (floating-point)
15.31 VPOP (floating-point)
15.32 VPUSH (floating-point)
15.33 VRINT (floating-point)
15.34 VSEL
15.35 VSQRT
15.36 VSTM (floating-point)
15.37 VSTR (floating-point)
15.38 VSTR (post-increment and pre-decrement, floating-point)
15.39 VSUB (floating-point)
16 A64 General Instructions
16.1 A64 general instructions in alphabetical order
16.2 Register restrictions for A64 instructions
16.3 ADC
16.4 ADCS
16.5 ADD (extended register)
16.6 ADD (immediate)
16.7 ADD (shifted register)
16.8 ADDS (extended register)
16.9 ADDS (immediate)
16.10 ADDS (shifted register)
16.11 ADR
16.12 ADRL pseudo-instruction
16.13 ADRP
16.14 AND (immediate)
16.15 AND (shifted register)
16.16 ANDS (immediate)
16.17 ANDS (shifted register)
16.18 ASR (register)
16.19 ASR (immediate)
16.20 ASRV
16.21 AT
16.22 B.
16.23 B
16.24 BFI
16.25 BFM
16.26 BFXIL
16.27 BIC (shifted register)
16.28 BICS (shifted register)
16.29 BL
16.30 BLR
16.31 BR
16.32 BRK
16.33 CBNZ
16.34 CBZ
16.35 CCMN (immediate)
16.36 CCMN (register)
16.37 CCMP (immediate)
16.38 CCMP (register)
16.39 CINC
16.40 CINV
16.41 CLREX
16.42 CLS
16.43 CLZ
16.44 CMN (extended register)
16.45 CMN (immediate)
16.46 CMN (shifted register)
16.47 CMP (extended register)
16.48 CMP (immediate)
16.49 CMP (shifted register)
16.50 CNEG
16.51 CRC32B, CRC32H, CRC32W, CRC32X
16.52 CRC32CB, CRC32CH, CRC32CW, CRC32CX
16.53 CSEL
16.54 CSET
16.55 CSETM
16.56 CSINC
16.57 CSINV
16.58 CSNEG
16.59 DC
16.60 DCPS1
16.61 DCPS2
16.62 DCPS3
16.63 DMB
16.64 DRPS
16.65 DSB
16.66 EON (shifted register)
16.67 EOR (immediate)
16.68 EOR (shifted register)
16.69 ERET
16.70 EXTR
16.71 HINT
16.72 HLT
16.73 HVC
16.74 IC
16.75 ISB
16.76 LSL (register)
16.77 LSL (immediate)
16.78 LSLV
16.79 LSR (register)
16.80 LSR (immediate)
16.81 LSRV
16.82 MADD
16.83 MNEG
16.84 MOV (to or from SP)
16.85 MOV (inverted wide immediate)
16.86 MOV (wide immediate)
16.87 MOV (bitmask immediate)
16.88 MOV (register)
16.89 MOVK
16.90 MOVL pseudo-instruction
16.91 MOVN
16.92 MOVZ
16.93 MRS
16.94 MSR (immediate)
16.95 MSR (register)
16.96 MSUB
16.97 MUL
16.98 MVN
16.99 NEG (shifted register)
16.100 NEGS
16.101 NGC
16.102 NGCS
16.103 NOP
16.104 ORN (shifted register)
16.105 ORR (immediate)
16.106 ORR (shifted register)
16.107 RBIT
16.108 RET
16.109 REV16
16.110 REV32
16.111 REV
16.112 ROR (immediate)
16.113 ROR (register)
16.114 RORV
16.115 SBC
16.116 SBCS
16.117 SBFIZ
16.118 SBFM
16.119 SBFX
16.120 SDIV
16.121 SEV
16.122 SEVL
16.123 SMADDL
16.124 SMC
16.125 SMNEGL
16.126 SMSUBL
16.127 SMULH
16.128 SMULL
16.129 SUB (extended register)
16.130 SUB (immediate)
16.131 SUB (shifted register)
16.132 SUBS (extended register)
16.133 SUBS (immediate)
16.134 SUBS (shifted register)
16.135 SVC
16.136 SXTB
16.137 SXTH
16.138 SXTW
16.139 SYS
16.140 SYSL
16.141 TBNZ
16.142 TBZ
16.143 TLBI
16.144 TST (immediate)
16.145 TST (shifted register)
16.146 UBFIZ
16.147 UBFM
16.148 UBFX
16.149 UDIV
16.150 UMADDL
16.151 UMNEGL
16.152 UMSUBL
16.153 UMULH
16.154 UMULL
16.155 UXTB
16.156 UXTH
16.157 WFE
16.158 WFI
16.159 YIELD
17 A64 Data Transfer Instructions
17.1 A64 data transfer instructions in alphabetical order
17.2 Register restrictions for A64 instructions
17.3 LDAR
17.4 LDARB
17.5 LDARH
17.6 LDAXP
17.7 LDAXR
17.8 LDAXRB
17.9 LDAXRH
17.10 LDNP (SIMD and FP)
17.11 LDNP
17.12 LDP (SIMD and FP)
17.13 LDP
17.14 LDPSW
17.15 LDR (immediate, SIMD and FP)
17.16 LDR (immediate)
17.17 LDR (literal, SIMD and FP)
17.18 LDR (literal)
17.19 LDR pseudo-instruction
17.20 LDR (register, SIMD and FP)
17.21 LDR (register)
17.22 LDRB (immediate)
17.23 LDRB (register)
17.24 LDRH (immediate)
17.25 LDRH (register)
17.26 LDRSB (immediate)
17.27 LDRSB (register)
17.28 LDRSH (immediate)
17.29 LDRSH (register)
17.30 LDRSW (immediate)
17.31 LDRSW (literal)
17.32 LDRSW (register)
17.33 LDTR
17.34 LDTRB
17.35 LDTRH
17.36 LDTRSB
17.37 LDTRSH
17.38 LDTRSW
17.39 LDUR (SIMD and FP)
17.40 LDUR
17.41 LDURB
17.42 LDURH
17.43 LDURSB
17.44 LDURSH
17.45 LDURSW
17.46 LDXP
17.47 LDXR
17.48 LDXRB
17.49 LDXRH
17.50 PRFM (immediate)
17.51 PRFM (literal)
17.52 PRFM (register)
17.53 PRFUM
17.54 STLR
17.55 STLRB
17.56 STLRH
17.57 STLXP
17.58 STLXR
17.59 STLXRB
17.60 STLXRH
17.61 STNP (SIMD and FP)
17.62 STNP
17.63 STP (SIMD and FP)
17.64 STP
17.65 STR (immediate, SIMD and FP)
17.66 STR (immediate)
17.67 STR (register, SIMD and FP)
17.68 STR (register)
17.69 STRB (immediate)
17.70 STRB (register)
17.71 STRH (immediate)
17.72 STRH (register)
17.73 STTR
17.74 STTRB
17.75 STTRH
17.76 STUR (SIMD and FP)
17.77 STUR
17.78 STURB
17.79 STURH
17.80 STXP
17.81 STXR
17.82 STXRB
17.83 STXRH
18 A64 Floating-point Instructions
18.1 A64 floating-point instructions in alphabetical order
18.2 FABS (scalar)
18.3 FADD (scalar)
18.4 FCCMP
18.5 FCCMPE
18.6 FCMP
18.7 FCMPE
18.8 FCSEL
18.9 FCVT
18.10 FCVTAS (scalar)
18.11 FCVTAU (scalar)
18.12 FCVTMS (scalar)
18.13 FCVTMU (scalar)
18.14 FCVTNS (scalar)
18.15 FCVTNU (scalar)
18.16 FCVTPS (scalar)
18.17 FCVTPU (scalar)
18.18 FCVTZS (scalar, fixed-point)
18.19 FCVTZS (scalar, integer)
18.20 FCVTZU (scalar, fixed-point)
18.21 FCVTZU (scalar, integer)
18.22 FDIV (scalar)
18.23 FMADD
18.24 FMAX (scalar)
18.25 FMAXNM (scalar)
18.26 FMIN (scalar)
18.27 FMINNM (scalar)
18.28 FMOV (register)
18.29 FMOV (general)
18.30 FMOV (scalar, immediate)
18.31 FMSUB
18.32 FMUL (scalar)
18.33 FNEG (scalar)
18.34 FNMADD
18.35 FNMSUB
18.36 FNMUL
18.37 FRINTA (scalar)
18.38 FRINTI (scalar)
18.39 FRINTM (scalar)
18.40 FRINTN (scalar)
18.41 FRINTP (scalar)
18.42 FRINTX (scalar)
18.43 FRINTZ (scalar)
18.44 FSQRT (scalar)
18.45 FSUB (scalar)
18.46 SCVTF (scalar, fixed-point)
18.47 SCVTF (scalar, integer)
18.48 UCVTF (scalar, fixed-point)
18.49 UCVTF (scalar, integer)
19 A64 SIMD Scalar Instructions
19.1 A64 SIMD scalar instructions in alphabetical order
19.2 ABS (scalar)
19.3 ADD (scalar)
19.4 ADDP (scalar)
19.5 CMEQ (scalar, register)
19.6 CMEQ (scalar, zero)
19.7 CMGE (scalar, register)
19.8 CMGE (scalar, zero)
19.9 CMGT (scalar, register)
19.10 CMGT (scalar, zero)
19.11 CMHI (scalar, register)
19.12 CMHS (scalar, register)
19.13 CMLE (scalar, zero)
19.14 CMLT (scalar, zero)
19.15 CMTST (scalar)
19.16 DUP (scalar, element)
19.17 FABD (scalar)
19.18 FACGE (scalar)
19.19 FACGT (scalar)
19.20 FADDP (scalar)
19.21 FCMEQ (scalar, register)
19.22 FCMEQ (scalar, zero)
19.23 FCMGE (scalar, register)
19.24 FCMGE (scalar, zero)
19.25 FCMGT (scalar, register)
19.26 FCMGT (scalar, zero)
19.27 FCMLE (scalar, zero)
19.28 FCMLT (scalar, zero)
19.29 FCVTAS (scalar)
19.30 FCVTAU (scalar)
19.31 FCVTMS (scalar)
19.32 FCVTMU (scalar)
19.33 FCVTNS (scalar)
19.34 FCVTNU (scalar)
19.35 FCVTPS (scalar)
19.36 FCVTPU (scalar)
19.37 FCVTXN (scalar)
19.38 FCVTZS (scalar, fixed-point)
19.39 FCVTZS (scalar, integer)
19.40 FCVTZU (scalar, fixed-point)
19.41 FCVTZU (scalar, integer)
19.42 FMAXNMP (scalar)
19.43 FMAXP (scalar)
19.44 FMINNMP (scalar)
19.45 FMINP (scalar)
19.46 FMLA (scalar, by element)
19.47 FMLS (scalar, by element)
19.48 FMUL (scalar, by element)
19.49 FMULX (scalar, by element)
19.50 FMULX (scalar)
19.51 FRECPE (scalar)
19.52 FRECPS (scalar)
19.53 FRECPX (scalar)
19.54 FRSQRTE (scalar)
19.55 FRSQRTS (scalar)
19.56 MOV (scalar)
19.57 NEG (scalar)
19.58 SCVTF (scalar, fixed-point)
19.59 SCVTF (scalar, integer)
19.60 SHL (scalar)
19.61 SLI (scalar)
19.62 SQABS (scalar)
19.63 SQADD (scalar)
19.64 SQDMLAL (scalar, by element)
19.65 SQDMLAL (scalar)
19.66 SQDMLSL (scalar, by element)
19.67 SQDMLSL (scalar)
19.68 SQDMULH (scalar, by element)
19.69 SQDMULH (scalar)
19.70 SQDMULL (scalar, by element)
19.71 SQDMULL (scalar)
19.72 SQNEG (scalar)
19.73 SQRDMULH (scalar, by element)
19.74 SQRDMULH (scalar)
19.75 SQRSHL (scalar)
19.76 SQRSHRN (scalar)
19.77 SQRSHRUN (scalar)
19.78 SQSHL (scalar, immediate)
19.79 SQSHL (scalar, register)
19.80 SQSHLU (scalar)
19.81 SQSHRN (scalar)
19.82 SQSHRUN (scalar)
19.83 SQSUB (scalar)
19.84 SQXTN (scalar)
19.85 SQXTUN (scalar)
19.86 SRI (scalar)
19.87 SRSHL (scalar)
19.88 SRSHR (scalar)
19.89 SRSRA (scalar)
19.90 SSHL (scalar)
19.91 SSHR (scalar)
19.92 SSRA (scalar)
19.93 SUB (scalar)
19.94 SUQADD (scalar)
19.95 UCVTF (scalar, fixed-point)
19.96 UCVTF (scalar, integer)
19.97 UQADD (scalar)
19.98 UQRSHL (scalar)
19.99 UQRSHRN (scalar)
19.100 UQSHL (scalar, immediate)
19.101 UQSHL (scalar, register)
19.102 UQSHRN (scalar)
19.103 UQSUB (scalar)
19.104 UQXTN (scalar)
19.105 URSHL (scalar)
19.106 URSHR (scalar)
19.107 URSRA (scalar)
19.108 USHL (scalar)
19.109 USHR (scalar)
19.110 USQADD (scalar)
19.111 USRA (scalar)
20 A64 SIMD Vector Instructions
20.1 A64 SIMD Vector instructions in alphabetical order
20.2 ABS (vector)
20.3 ADD (vector)
20.4 ADDHN, ADDHN2 (vector)
20.5 ADDP (vector)
20.6 ADDV (vector)
20.7 AND (vector)
20.8 BIC (vector, immediate)
20.9 BIC (vector, register)
20.10 BIF (vector)
20.11 BIT (vector)
20.12 BSL (vector)
20.13 CLS (vector)
20.14 CLZ (vector)
20.15 CMEQ (vector, register)
20.16 CMEQ (vector, zero)
20.17 CMGE (vector, register)
20.18 CMGE (vector, zero)
20.19 CMGT (vector, register)
20.20 CMGT (vector, zero)
20.21 CMHI (vector, register)
20.22 CMHS (vector, register)
20.23 CMLE (vector, zero)
20.24 CMLT (vector, zero)
20.25 CMTST (vector)
20.26 CNT (vector)
20.27 DUP (vector, element)
20.28 DUP (vector, general)
20.29 EOR (vector)
20.30 EXT (vector)
20.31 FABD (vector)
20.32 FABS (vector)
20.33 FACGE (vector)
20.34 FACGT (vector)
20.35 FADD (vector)
20.36 FADDP (vector)
20.37 FCMEQ (vector, register)
20.38 FCMEQ (vector, zero)
20.39 FCMGE (vector, register)
20.40 FCMGE (vector, zero)
20.41 FCMGT (vector, register)
20.42 FCMGT (vector, zero)
20.43 FCMLE (vector, zero)
20.44 FCMLT (vector, zero)
20.45 FCVTAS (vector)
20.46 FCVTAU (vector)
20.47 FCVTL, FCVTL2 (vector)
20.48 FCVTMS (vector)
20.49 FCVTMU (vector)
20.50 FCVTN, FCVTN2 (vector)
20.51 FCVTNS (vector)
20.52 FCVTNU (vector)
20.53 FCVTPS (vector)
20.54 FCVTPU (vector)
20.55 FCVTXN, FCVTXN2 (vector)
20.56 FCVTZS (vector, fixed-point)
20.57 FCVTZS (vector, integer)
20.58 FCVTZU (vector, fixed-point)
20.59 FCVTZU (vector, integer)
20.60 FDIV (vector)
20.61 FMAX (vector)
20.62 FMAXNM (vector)
20.63 FMAXNMP (vector)
20.64 FMAXNMV (vector)
20.65 FMAXP (vector)
20.66 FMAXV (vector)
20.67 FMIN (vector)
20.68 FMINNM (vector)
20.69 FMINNMP (vector)
20.70 FMINNMV (vector)
20.71 FMINP (vector)
20.72 FMINV (vector)
20.73 FMLA (vector, by element)
20.74 FMLA (vector)
20.75 FMLS (vector, by element)
20.76 FMLS (vector)
20.77 FMOV (vector, immediate)
20.78 FMUL (vector, by element)
20.79 FMUL (vector)
20.80 FMULX (vector, by element)
20.81 FMULX (vector)
20.82 FNEG (vector)
20.83 FRECPE (vector)
20.84 FRECPS (vector)
20.85 FRINTA (vector)
20.86 FRINTI (vector)
20.87 FRINTM (vector)
20.88 FRINTN (vector)
20.89 FRINTP (vector)
20.90 FRINTX (vector)
20.91 FRINTZ (vector)
20.92 FRSQRTE (vector)
20.93 FRSQRTS (vector)
20.94 FSQRT (vector)
20.95 FSUB (vector)
20.96 INS (vector, element)
20.97 INS (vector, general)
20.98 LD1 (vector, multiple structures)
20.99 LD1 (vector, single structure)
20.100 LD1R (vector)
20.101 LD2 (vector, multiple structures)
20.102 LD2 (vector, single structure)
20.103 LD2R (vector)
20.104 LD3 (vector, multiple structures)
20.105 LD3 (vector, single structure)
20.106 LD3R (vector)
20.107 LD4 (vector, multiple structures)
20.108 LD4 (vector, single structure)
20.109 LD4R (vector)
20.110 MLA (vector, by element)
20.111 MLA (vector)
20.112 MLS (vector, by element)
20.113 MLS (vector)
20.114 MOV (vector, element)
20.115 MOV (vector, from general)
20.116 MOV (vector)
20.117 MOV (vector, to general)
20.118 MOVI (vector)
20.119 MUL (vector, by element)
20.120 MUL (vector)
20.121 MVN (vector)
20.122 MVNI (vector)
20.123 NEG (vector)
20.124 NOT (vector)
20.125 ORN (vector)
20.126 ORR (vector, immediate)
20.127 ORR (vector, register)
20.128 PMUL (vector)
20.129 PMULL, PMULL2 (vector)
20.130 RADDHN, RADDHN2 (vector)
20.131 RBIT (vector)
20.132 REV16 (vector)
20.133 REV32 (vector)
20.134 REV64 (vector)
20.135 RSHRN, RSHRN2 (vector)
20.136 RSUBHN, RSUBHN2 (vector)
20.137 SABA (vector)
20.138 SABAL, SABAL2 (vector)
20.139 SABD (vector)
20.140 SABDL, SABDL2 (vector)
20.141 SADALP (vector)
20.142 SADDL, SADDL2 (vector)
20.143 SADDLP (vector)
20.144 SADDLV (vector)
20.145 SADDW, SADDW2 (vector)
20.146 SCVTF (vector, fixed-point)
20.147 SCVTF (vector, integer)
20.148 SHADD (vector)
20.149 SHL (vector)
20.150 SHLL, SHLL2 (vector)
20.151 SHRN, SHRN2 (vector)
20.152 SHSUB (vector)
20.153 SLI (vector)
20.154 SMAX (vector)
20.155 SMAXP (vector)
20.156 SMAXV (vector)
20.157 SMIN (vector)
20.158 SMINP (vector)
20.159 SMINV (vector)
20.160 SMLAL, SMLAL2 (vector, by element)
20.161 SMLAL, SMLAL2 (vector)
20.162 SMLSL, SMLSL2 (vector, by element)
20.163 SMLSL, SMLSL2 (vector)
20.164 SMOV (vector)
20.165 SMULL, SMULL2 (vector, by element)
20.166 SMULL, SMULL2 (vector)
20.167 SQABS (vector)
20.168 SQADD (vector)
20.169 SQDMLAL, SQDMLAL2 (vector, by element)
20.170 SQDMLAL, SQDMLAL2 (vector)
20.171 SQDMLSL, SQDMLSL2 (vector, by element)
20.172 SQDMLSL, SQDMLSL2 (vector)
20.173 SQDMULH (vector, by element)
20.174 SQDMULH (vector)
20.175 SQDMULL, SQDMULL2 (vector, by element)
20.176 SQDMULL, SQDMULL2 (vector)
20.177 SQNEG (vector)
20.178 SQRDMULH (vector, by element)
20.179 SQRDMULH (vector)
20.180 SQRSHL (vector)
20.181 SQRSHRN, SQRSHRN2 (vector)
20.182 SQRSHRUN, SQRSHRUN2 (vector)
20.183 SQSHL (vector, immediate)
20.184 SQSHL (vector, register)
20.185 SQSHLU (vector)
20.186 SQSHRN, SQSHRN2 (vector)
20.187 SQSHRUN, SQSHRUN2 (vector)
20.188 SQSUB (vector)
20.189 SQXTN, SQXTN2 (vector)
20.190 SQXTUN, SQXTUN2 (vector)
20.191 SRHADD (vector)
20.192 SRI (vector)
20.193 SRSHL (vector)
20.194 SRSHR (vector)
20.195 SRSRA (vector)
20.196 SSHL (vector)
20.197 SSHLL, SSHLL2 (vector)
20.198 SSHR (vector)
20.199 SSRA (vector)
20.200 SSUBL, SSUBL2 (vector)
20.201 SSUBW, SSUBW2 (vector)
20.202 ST1 (vector, multiple structures)
20.203 ST1 (vector, single structure)
20.204 ST2 (vector, multiple structures)
20.205 ST2 (vector, single structure)
20.206 ST3 (vector, multiple structures)
20.207 ST3 (vector, single structure)
20.208 ST4 (vector, multiple structures)
20.209 ST4 (vector, single structure)
20.210 SUB (vector)
20.211 SUBHN, SUBHN2 (vector)
20.212 SUQADD (vector)
20.213 SXTL, SXTL2 (vector)
20.214 TBL (vector)
20.215 TBX (vector)
20.216 TRN1 (vector)
20.217 TRN2 (vector)
20.218 UABA (vector)
20.219 UABAL, UABAL2 (vector)
20.220 UABD (vector)
20.221 UABDL, UABDL2 (vector)
20.222 UADALP (vector)
20.223 UADDL, UADDL2 (vector)
20.224 UADDLP (vector)
20.225 UADDLV (vector)
20.226 UADDW, UADDW2 (vector)
20.227 UCVTF (vector, fixed-point)
20.228 UCVTF (vector, integer)
20.229 UHADD (vector)
20.230 UHSUB (vector)
20.231 UMAX (vector)
20.232 UMAXP (vector)
20.233 UMAXV (vector)
20.234 UMIN (vector)
20.235 UMINP (vector)
20.236 UMINV (vector)
20.237 UMLAL, UMLAL2 (vector, by element)
20.238 UMLAL, UMLAL2 (vector)
20.239 UMLSL, UMLSL2 (vector, by element)
20.240 UMLSL, UMLSL2 (vector)
20.241 UMOV (vector)
20.242 UMULL, UMULL2 (vector, by element)
20.243 UMULL, UMULL2 (vector)
20.244 UQADD (vector)
20.245 UQRSHL (vector)
20.246 UQRSHRN, UQRSHRN2 (vector)
20.247 UQSHL (vector, immediate)
20.248 UQSHL (vector, register)
20.249 UQSHRN, UQSHRN2 (vector)
20.250 UQSUB (vector)
20.251 UQXTN, UQXTN2 (vector)
20.252 URECPE (vector)
20.253 URHADD (vector)
20.254 URSHL (vector)
20.255 URSHR (vector)
20.256 URSQRTE (vector)
20.257 URSRA (vector)
20.258 USHL (vector)
20.259 USHLL, USHLL2 (vector)
20.260 USHR (vector)
20.261 USQADD (vector)
20.262 USRA (vector)
20.263 USUBL, USUBL2 (vector)
20.264 USUBW, USUBW2 (vector)
20.265 UXTL, UXTL2 (vector)
20.266 UZP1 (vector)
20.267 UZP2 (vector)
20.268 XTN, XTN2 (vector)
20.269 ZIP1 (vector)
20.270 ZIP2 (vector)
21 Directives Reference
21.1 Alphabetical list of directives
21.2 About assembly control directives
21.3 About frame directives
21.4 ALIAS
21.5 ALIGN
21.6 AREA
21.7 ARM or CODE32 directive
21.8 ASSERT
21.9 ATTR
21.10 CN
21.11 CODE16 directive
21.12 COMMON
21.13 CP
21.14 DATA
21.15 DCB
21.16 DCD and DCDU
21.17 DCDO
21.18 DCFD and DCFDU
21.19 DCFS and DCFSU
21.20 DCI
21.21 DCQ and DCQU
21.22 DCW and DCWU
21.23 END
21.24 ENDFUNC or ENDP
21.25 ENTRY
21.26 EQU
21.27 EXPORT or GLOBAL
21.28 EXPORTAS
21.29 FIELD
21.30 FRAME ADDRESS
21.31 FRAME POP
21.32 FRAME PUSH
21.33 FRAME REGISTER
21.34 FRAME RESTORE
21.35 FRAME RETURN ADDRESS
21.36 FRAME SAVE
21.37 FRAME STATE REMEMBER
21.38 FRAME STATE RESTORE
21.39 FRAME UNWIND ON
21.40 FRAME UNWIND OFF
21.41 FUNCTION or PROC
21.42 GBLA, GBLL, and GBLS
21.43 GET or INCLUDE
21.44 IF, ELSE, ENDIF, and ELIF
21.45 IMPORT and EXTERN
21.46 INCBIN
21.47 INFO
21.48 KEEP
21.49 LCLA, LCLL, and LCLS
21.50 LTORG
21.51 MACRO and MEND
21.52 MAP
21.53 MEXIT
21.54 NOFP
21.55 OPT
21.56 QN, DN, and SN
21.57 RELOC
21.58 REQUIRE
21.59 REQUIRE8 and PRESERVE8
21.60 RLIST
21.61 RN
21.62 ROUT
21.63 SETA, SETL, and SETS
21.64 SPACE or FILL
21.65 THUMB directive
21.66 TTL and SUBT
21.67 WHILE and WEND
21.68 WN and XN
22 Via File Syntax
22.1 Overview of via files
22.2 Via file syntax rules

List of Figures

1-1 Integration boundaries in ARM Compiler 6.
3-1 Organization of general-purpose registers and Program Status Registers
9-1 Extension register bank for Advanced SIMD in AArch32 state
9-2 Extension register bank for Advanced SIMD in AArch64 state
10-1 Extension register bank for floating-point in AArch32 state
10-2 Extension register bank for floating-point in AArch64 state
13-1 ASR #3
13-2 LSR #3
13-3 LSL #3
13-4 ROR #3
13-5 RRX
14-1 De-interleaving an array of 3-element structures
14-2 Operation of doubleword VEXT for imm = 3
14-3 Example of operation of VPADAL (in this case for data type S16)
14-4 Example of operation of VPADD (in this case, for data type I16)
14-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
14-6 Operation of quadword VSHL.I64 Qd, Qm, #1
14-7 Operation of quadword VSLI.64 Qd, Qm, #1
14-8 Operation of doubleword VSRI.64 Dd, Dm, #2
14-9 Operation of doubleword VTRN.8
14-10 Operation of doubleword VTRN.32

List of Tables

3-1 ARM processor modes
3-2 Predeclared core registers in AArch32 state
3-3 Predeclared extension registers in AArch32 state
3-4 A32 instruction groups
4-1 Predeclared core registers in AArch64 state
4-2 Predeclared extension registers in AArch64 state
4-3 A64 instruction groups
6-1 Syntax differences between UAL and A64 assembly language
6-2 A32 state immediate values (8-bit)
6-3 A32 state immediate values in MOV instructions
6-4 32-bit T32 immediate values
6-5 32-bit T32 immediate values in MOV instructions
6-6 Stack-oriented suffixes and equivalent addressing mode suffixes
6-7 Suffixes for load and store multiple instructions
7-1 Condition code suffixes
7-2 Condition code suffixes and related flags
7-3 Condition codes
7-4 Conditional branches only
7-5 All instructions conditional
8-1 Built-in variables
8-2 Built-in Boolean constants
8-3 Predefined macros
8-4 armclang equivalent command-line options
9-1 Differences in syntax and mnemonics between A32/T32 and A64 Advanced SIMD instructions
9-2 Advanced SIMD data types
9-3 Advanced SIMD saturation ranges
10-1 Differences in syntax and mnemonics between A32/T32 and A64 floating-point instructions
11-1 Supported ARM architectures
11-2 Severity of diagnostic messages
11-3 Specifying a command-line option and an AREA directive for GNU-stack sections
12-1 Unary operators that return strings
12-2 Unary operators that return numeric or logical values
12-3 Multiplicative operators
12-4 String manipulation operators
12-5 Shift operators
12-6 Addition, subtraction, and logical operators
12-7 Relational operators
12-8 Boolean operators
12-9 Operator precedence in ARM assembly language
12-10 Operator precedence in C
13-1 Summary of instructions
13-2 PC-relative offsets
13-3 Register-relative offsets
13-4 B instruction availability and range
13-5 BL instruction availability and range
13-6 BLX instruction availability and range
13-7 BX instruction availability and range
13-8 BXJ instruction availability and range
13-9 Permitted instructions inside an IT block
13-10 Offsets and architectures, LDR, word, halfword, and byte
13-11 PC-relative offsets
13-12 Options and architectures, LDR (register offsets)
13-13 Register-relative offsets
13-14 Offsets and architectures, LDR (User mode)
13-15 Offsets and architectures, STR, word, halfword, and byte
13-16 Options and architectures, STR (register offsets)
13-17 Offsets and architectures, STR (User mode)
13-18 Range and encoding of expr
14-1 Summary of Advanced SIMD instructions
14-2 Summary of shared Advanced SIMD and floating-point instructions
14-3 Patterns for immediate value in VBIC (immediate)
14-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
14-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
14-6 Permitted combinations of parameters for VLDn (multiple n-element structures)
14-7 Available immediate values in VMOV (immediate)
14-8 Available immediate values in VMVN (immediate)
14-9 Patterns for immediate value in VORR (immediate)
14-10 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
14-11 Available immediate ranges in VQSHL and VQSHLU (by immediate)
14-12 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
14-13 Results for out-of-range inputs in VRECPE
14-14 Results for out-of-range inputs in VRECPS
14-15 Available immediate ranges in VRSHR (by immediate)
14-16 Available immediate ranges in VRSHRN (by immediate)
14-17 Results for out-of-range inputs in VRSQRTE
14-18 Results for out-of-range inputs in VRSQRTS
14-19 Available immediate ranges in VRSRA (by immediate)
14-20 Available immediate ranges in VSHL (by immediate)
14-21 Available immediate ranges in VSHLL (by immediate)
14-22 Available immediate ranges in VSHR (by immediate)
14-23 Available immediate ranges in VSHRN (by immediate)
14-24 Available immediate ranges in VSRA (by immediate)
14-25 Permitted combinations of parameters for VSTn (multiple n-element structures)
14-26 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
14-27 Operation of doubleword VUZP.8
14-28 Operation of quadword VUZP.32
14-29 Operation of doubleword VZIP.8
14-30 Operation of quadword VZIP.32
15-1 Summary of floating-point instructions
16-1 Summary of A64 general instructions
16-2 ADD (64-bit general registers) specifier combinations
16-3 ADDS (64-bit general registers) specifier combinations
16-4 SYS parameter values corresponding to AT operations
16-5 CMN (64-bit general registers) specifier combinations
16-6 CMP (64-bit general registers) specifier combinations
16-7 SYS parameter values corresponding to DC operations
16-8 HINT parameter values corresponding to the aliases
16-9 SYS parameter values corresponding to IC operations
16-10 SUB (64-bit general registers) specifier combinations
16-11 SUBS (64-bit general registers) specifier combinations
16-12 SYS parameter values corresponding to TLBI operations
17-1 Summary of A64 data transfer instructions
17-2 LDR (register, SIMD and FP) specifier combinations
17-3 LDR (register) specifier combinations
17-4 LDRB specifier combinations
17-5 LDRH specifier combinations
17-6 LDRSB (register) specifier combinations
17-7 LDRSH (register) specifier combinations
17-8 LDRSW specifier combinations
17-9 PRFM (immediate) type options
17-10 PRFM (immediate) target options
17-11 PRFM (immediate) policy options
17-12 PRFM (literal) type options
17-13 PRFM (literal) target options
17-14 PRFM (literal) policy options
17-15 PRFM (register) type options
17-16 PRFM (register) target options
17-17 PRFM (register) policy options
17-18 PRFM specifier combinations
17-19 PRFUM type options
17-20 PRFUM target options
17-21 PRFUM policy options
17-22 STR (register, SIMD and FP) specifier combinations
17-23 STR (register) specifier combinations
17-24 STRB specifier combinations
17-25 STRH specifier combinations
18-1 Summary of A64 floating-point instructions
19-1 Summary of A64 SIMD scalar instructions
19-2 DUP (Scalar) specifier combinations
19-3 FADDP (Scalar) specifier combinations
19-4 FCVTZS (Scalar) specifier combinations
19-5 FCVTZU (Scalar) specifier combinations
19-6 FMAXNMP (Scalar) specifier combinations
19-7 FMAXP (Scalar) specifier combinations
19-8 FMINNMP (Scalar) specifier combinations
19-9 FMINP (Scalar) specifier combinations
19-10 FMLA (Scalar) specifier combinations
19-11 FMLS (Scalar) specifier combinations
19-12 FMUL (Scalar) specifier combinations
19-13 FMULX (Scalar) specifier combinations
19-14 MOV (Scalar) specifier combinations
19-15 SCVTF (Scalar) specifier combinations
19-16 SQDMLAL (Scalar) specifier combinations
19-17 SQDMLAL (Scalar) specifier combinations
19-18 SQDMLSL (Scalar) specifier combinations
19-19 SQDMLSL (Scalar) specifier combinations
19-20 SQDMULH (Scalar) specifier combinations
19-21 SQDMULL (Scalar) specifier combinations
19-22 SQDMULL (Scalar) specifier combinations
19-23 SQRDMULH (Scalar) specifier combinations
19-24 SQRSHRN (Scalar) specifier combinations
19-25 SQRSHRUN (Scalar) specifier combinations
19-26 SQSHL (Scalar) specifier combinations
19-27 SQSHLU (Scalar) specifier combinations
19-28 SQSHRN (Scalar) specifier combinations
19-29 SQSHRUN (Scalar) specifier combinations
19-30 SQXTN (Scalar) specifier combinations
19-31 SQXTUN (Scalar) specifier combinations
19-32 UCVTF (Scalar) specifier combinations
19-33 UQRSHRN (Scalar) specifier combinations
19-34 UQSHL (Scalar) specifier combinations
19-35 UQSHRN (Scalar) specifier combinations
19-36 UQXTN (Scalar) specifier combinations
20-1 Summary of A64 SIMD Vector instructions
20-2 ADDHN, ADDHN2 (Vector) specifier combinations
20-3 ADDV (Vector) specifier combinations
20-4 DUP (Vector) specifier combinations
20-5 DUP (Vector) specifier combinations
20-6 EXT (Vector) specifier combinations
20-7 FCVTL, FCVTL2 (Vector) specifier combinations
20-8 FCVTN, FCVTN2 (Vector) specifier combinations
20-9 FCVTXN{2} (Vector) specifier combinations
20-10 FCVTZS (Vector) specifier combinations
20-11 FCVTZU (Vector) specifier combinations
20-12 FMLA (Vector) specifier combinations
20-13 FMLS (Vector) specifier combinations
20-14 FMUL (Vector) specifier combinations
20-15 FMULX (Vector) specifier combinations
20-16 INS (Vector) specifier combinations
20-17 INS (Vector) specifier combinations
20-18 LD1 (One register, immediate offset) specifier combinations
20-19 LD1 (Two registers, immediate offset) specifier combinations
20-20 LD1 (Three registers, immediate offset) specifier combinations
20-21 LD1 (Four registers, immediate offset) specifier combinations
20-22 LD1R (Immediate offset) specifier combinations
20-23 LD2R (Immediate offset) specifier combinations
20-24 LD3R (Immediate offset) specifier combinations
20-25 LD4R (Immediate offset) specifier combinations
20-26 MLA (Vector) specifier combinations
20-27 MLS (Vector) specifier combinations
20-28 MOV (Vector) specifier combinations
20-29 MOV (Vector) specifier combinations
20-30 MUL (Vector) specifier combinations
20-31 PMULL, PMULL2 (Vector) specifier combinations
20-32 RADDHN, RADDHN2 (Vector) specifier combinations
20-33 RSHRN, RSHRN2 (Vector) specifier combinations
20-34 RSUBHN, RSUBHN2 (Vector) specifier combinations
20-35 SABAL, SABAL2 (Vector) specifier combinations
20-36 SABDL, SABDL2 (Vector) specifier combinations
20-37 SADALP (Vector) specifier combinations
20-38 SADDL, SADDL2 (Vector) specifier combinations
20-39 SADDLP (Vector) specifier combinations
20-40 SADDLV (Vector) specifier combinations
20-41 SADDW, SADDW2 (Vector) specifier combinations
20-42 SCVTF (Vector) specifier combinations
20-43 SHL (Vector) specifier combinations
20-44 SHLL, SHLL2 (Vector) specifier combinations
20-45 SHRN, SHRN2 (Vector) specifier combinations
20-46 SLI (Vector) specifier combinations
20-47 SMAXV (Vector) specifier combinations
20-48 SMINV (Vector) specifier combinations
20-49 SMLAL, SMLAL2 (Vector) specifier combinations
20-50 SMLAL, SMLAL2 (Vector) specifier combinations
20-51 SMLSL, SMLSL2 (Vector) specifier combinations
20-52 SMLSL, SMLSL2 (Vector) specifier combinations
20-53 SMOV (32-bit) specifier combinations
20-54 SMOV (64-bit) specifier combinations
20-55 SMULL, SMULL2 (Vector) specifier combinations
20-56 SMULL, SMULL2 (Vector) specifier combinations
20-57 SQDMLAL{2} (Vector) specifier combinations
20-58 SQDMLAL{2} (Vector) specifier combinations
20-59 SQDMLSL{2} (Vector) specifier combinations
20-60 SQDMLSL{2} (Vector) specifier combinations
20-61 SQDMULH (Vector) specifier combinations
20-62 SQDMULL{2} (Vector) specifier combinations
20-63 SQDMULL{2} (Vector) specifier combinations
20-64 SQRDMULH (Vector) specifier combinations
20-65 SQRSHRN{2} (Vector) specifier combinations
20-66 SQRSHRUN{2} (Vector) specifier combinations
20-67 SQSHL (Vector) specifier combinations
20-68 SQSHLU (Vector) specifier combinations
20-69 SQSHRN{2} (Vector) specifier combinations
20-70 SQSHRUN{2} (Vector) specifier combinations
20-71 SQXTN{2} (Vector) specifier combinations
20-72 SQXTUN{2} (Vector) specifier combinations
20-73 SRI (Vector) specifier combinations
20-74 SRSHR (Vector) specifier combinations
20-75 SRSRA (Vector) specifier combinations
20-76 SSHLL, SSHLL2 (Vector) specifier combinations
20-77 SSHR (Vector) specifier combinations
20-78 SSRA (Vector) specifier combinations
20-79 SSUBL, SSUBL2 (Vector) specifier combinations
20-80 SSUBW, SSUBW2 (Vector) specifier combinations
20-81 ST1 (One register, immediate offset-T32) specifier combinations
20-82 ST1 (Two registers, immediate offset-T32) specifier combinations
20-83 ST1 (Three registers, immediate offset-T32) specifier combinations
20-84 ST1 (Four registers, immediate offset-T32) specifier combinations
20-85 SUBHN, SUBHN2 (Vector) specifier combinations
20-86 SXTL, SXTL2 (Vector) specifier combinations
20-87 UABAL, UABAL2 (Vector) specifier combinations
20-88 UABDL, UABDL2 (Vector) specifier combinations
20-89 UADALP (Vector) specifier combinations
20-90 UADDL, UADDL2 (Vector) specifier combinations
20-91 UADDLP (Vector) specifier combinations
20-92 UADDLV (Vector) specifier combinations
20-93 UADDW, UADDW2 (Vector) specifier combinations
20-94 UCVTF (Vector) specifier combinations
20-95 UMAXV (Vector) specifier combinations
20-96 UMINV (Vector) specifier combinations
20-97 UMLAL, UMLAL2 (Vector) specifier combinations
20-98 UMLAL, UMLAL2 (Vector) specifier combinations
20-99 UMLSL, UMLSL2 (Vector) specifier combinations
20-100 UMLSL, UMLSL2 (Vector) specifier combinations
20-101 UMOV (32-bit) specifier combinations
20-102 UMULL, UMULL2 (Vector) specifier combinations
20-103 UMULL, UMULL2 (Vector) specifier combinations
20-104 UQRSHRN{2} (Vector) specifier combinations
20-105 UQSHL (Vector) specifier combinations
20-106 UQSHRN{2} (Vector) specifier combinations
20-107 UQXTN{2} (Vector) specifier combinations
20-108 URSHR (Vector) specifier combinations
20-109 URSRA (Vector) specifier combinations
20-110 USHLL, USHLL2 (Vector) specifier combinations
20-111 USHR (Vector) specifier combinations
20-112 USRA (Vector) specifier combinations
20-113 USUBL, USUBL2 (Vector) specifier combinations
20-114 USUBW, USUBW2 (Vector) specifier combinations
20-115 UXTL, UXTL2 (Vector) specifier combinations
20-116 XTN, XTN2 (Vector) specifier combinations
21-1 List of directives
21-2 OPT directive settings

Release Information

Document History
Issue Date Confidentiality Change
A 14 March 2014 Non-Confidential ARM Compiler v6.00 Release
B 15 December 2014 Non-Confidential ARM Compiler v6.01 Release
C 30 June 2015 Non-Confidential ARM Compiler v6.02 Release
D 18 November 2015 Non-Confidential ARM Compiler v6.3 Release
E 24 February 2016 Non-Confidential ARM Compiler v6.4 Release

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