Arm Compiler armasm User Guide : 16.66 DC

16.66 DC

Data Cache operation.

This instruction is an alias of SYS.

The equivalent instruction is SYS #op1, C7, Cm, #op2, Xt.

DC <dc_op>, Xt

Where:

<dc_op>: Is a DC instruction name, as listed for the DC system instruction group, and can be one of the values shown in Usage.
op1: Is a 3-bit unsigned immediate, in the range 0 to 7.
Cm: Is a name Cm, with m in the range 0 to 15.
op2: Is a 3-bit unsigned immediate, in the range 0 to 7.
Xt: Is the 64-bit name of the general-purpose source register.

Data Cache operation. For more information, see A64 system instructions for cache maintenance in the Arm^® Architecture Reference Manual Arm^®v8, for Arm^®v8‑A architecture profile.

The following table shows the valid specifier combinations:

Table 16-7 SYS parameter values corresponding to DC operations

<dc_op>	`op1`	`Cm`	`op2`
CISW	0	14	2
CIVAC	3	14	1
CSW	0	10	2
CVAC	3	10	1
CVAP	3	12	1
CVAU	3	11	1
ISW	0	6	2
IVAC	0	6	1
ZVA	3	4	1

Non-Confidential	PDF version	DUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.