17.98 STLXR

Store-Release Exclusive Register.

Syntax

STLXR Ws, Wt, [Xn|SP{,#0}] ; 32-bit

STLXR Ws, Xt, [Xn|SP{,#0}] ; 64-bit

Where:

Wt
Is the 32-bit name of the general-purpose register to be transferred.
Xt
Is the 64-bit name of the general-purpose register to be transferred.
Ws
Is the 32-bit name of the general-purpose register into which the status result of the store exclusive is written. The value returned is.
0
If the operation updates memory.
1
If the operation fails to update memory.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

  • Memory is not updated.
  • Ws is not updated.

Accessing an address that is not aligned to the size of the data being accessed causes an Alignment fault Data Abort exception to be generated, subject to the following rules:

  • The exception is generated if the Exclusive Monitors for the current PE include all of the addresses associated with the virtual address region of size bytes starting at address. The immediately following memory write must be to the same addresses.
  • Otherwise, it is implementation defined whether the exception is generated.

Whether the detection of memory aborts happens before or after the check on the local Exclusive Monitor depends on the implementation. As a result a failure of the local monitor can occur on some implementations even if the memory access would give a memory abort.

Usage

Store-Release Exclusive Register stores a 32-bit word or a 64-bit doubleword to memory if the PE has exclusive access to the memory address, from two registers, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, and particularly STLXR.
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