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Home > Advanced SIMD Instructions (32-bit) > VREV16, VREV32, and VREV64 |

Vector Reverse within halfwords, words, or doublewords.

`VREV`

{`n`

}.`cond`

`size`

, `Qd`

`Qm`

`VREV`

{`n`

}.`cond`

`size`

, `Dd`

`Dm`

where:

`n`

must be one of

`16`

,`32`

, or`64`

.`cond`

is an optional condition code.

`size`

must be one of

`8`

,`16`

, or`32`

, and must be less than

.`n`

`Qd, Qm`

specifies the destination vector and the operand vector, for a quadword operation.

`Dd, Dm`

specifies the destination vector and the operand vector, for a doubleword operation.

`VREV16`

reverses the order of 8-bit elements within each halfword of the
vector, and places the result in the corresponding destination vector.

`VREV32`

reverses the order of 8-bit or 16-bit elements within each word of
the vector, and places the result in the corresponding destination vector.

`VREV64`

reverses the order of 8-bit, 16-bit, or 32-bit elements within each
doubleword of the vector, and places the result in the corresponding destination vector.