20.204 SSHLL, SSHLL2 (vector)

Signed Shift Left Long (immediate).

This instruction is used by the alias SXTL, SXTL2, SXTL, SXTL22.

Syntax

SSHLL{2} Vd.Ta, Vn.Tb, #shift

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the SIMD and FP source register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.
shift
Is the left shift amount, in the range 0 to the source element width in bits minus 1, and can be one of the values shown in Usage.

Usage

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD and FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD and FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-78 SSHLL, SSHLL2 (Vector) specifier combinations

<Q> Ta Tb shift
- 8H 8B 0 to 7
2 8H 16B 0 to 7
- 4S 4H 0 to 15
2 4S 8H 0 to 15
- 2D 2S 0 to 31
2 2D 4S 0 to 31
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