15.21 VMLA (floating-point)

Floating-point multiply accumulate.


VMLA{cond}.F32 Sd, Sn, Sm

VMLA{cond}.F64 Dd, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the result and operands.

Dd, Dn, Dm

are the double-precision registers for the result and operands.


The VMLA instruction multiplies the values in the operand registers, adds the value in the destination register, and places the final result in the destination register.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow, Underflow, Inexact, or Input Denormal exceptions.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.