20.111 LD4 (vector, single structure)

Load single 4-element structure to one lane of four registers.

Syntax

LD4 { Vt.B, Vt2.B, Vt3.B, Vt4.B }[index], [Xn|SP] ; 8-bit

LD4 { Vt.H, Vt2.H, Vt3.H, Vt4.H }[index], [Xn|SP] ; 16-bit

LD4 { Vt.S, Vt2.S, Vt3.S, Vt4.S }[index], [Xn|SP] ; 32-bit

LD4 { Vt.D, Vt2.D, Vt3.D, Vt4.D }[index], [Xn|SP] ; 64-bit

LD4 { Vt.B, Vt2.B, Vt3.B, Vt4.B }[index], [Xn|SP], #4 ; 8-bit, immediate offset, Post-index

LD4 { Vt.B, Vt2.B, Vt3.B, Vt4.B }[index], [Xn|SP], Xm ; 8-bit, register offset, Post-index

LD4 { Vt.H, Vt2.H, Vt3.H, Vt4.H }[index], [Xn|SP], #8 ; 16-bit, immediate offset, Post-index

LD4 { Vt.H, Vt2.H, Vt3.H, Vt4.H }[index], [Xn|SP], Xm ; 16-bit, register offset, Post-index

LD4 { Vt.S, Vt2.S, Vt3.S, Vt4.S }[index], [Xn|SP], #16 ; 32-bit, immediate offset, Post-index

LD4 { Vt.S, Vt2.S, Vt3.S, Vt4.S }[index], [Xn|SP], Xm ; 32-bit, register offset, Post-index

LD4 { Vt.D, Vt2.D, Vt3.D, Vt4.D }[index], [Xn|SP], #32 ; 64-bit, immediate offset, Post-index

LD4 { Vt.D, Vt2.D, Vt3.D, Vt4.D }[index], [Xn|SP], Xm ; 64-bit, register offset, Post-index

Where:

Vt
Is the name of the first or only SIMD and FP register to be transferred.
Vt2
Is the name of the second SIMD and FP register to be transferred.
Vt3
Is the name of the third SIMD and FP register to be transferred.
Vt4
Is the name of the fourth SIMD and FP register to be transferred.
index

The value depends on the instruction variant:

8-bit
Is the element index, in the range 0 to 15.
16-bit
Is the element index, in the range 0 to 7.
32-bit
Is the element index, in the range 0 to 3.
64-bit
Is the element index, and can be either 0 or 1.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR.

Usage

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD and FP registers without affecting the other bits of the registers.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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