13.41 ESB

Error Synchronization Barrier.

Syntax

ESB{c}{q} ; A1 general registers (A32)

ESB{c}.W ; T1 general registers (T32)

Where:

q
Is an optional instruction width specifier. See 13.2 Instruction width specifiers.
c
Is an optional instruction condition code. See Chapter 7 Condition Codes.

Architectures supported

Supported in the Arm®v8‑A and Armv8‑R architectures.

Usage

Error Synchronization Barrier.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.