19.17 FABD (scalar)

Floating-point Absolute Difference (vector).

Syntax

FABD Hd, Hn, Hm ; Scalar half precision

FABD Vd, Vn, Vm ; Scalar single-precision and double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Hn
Is the 16-bit name of the first SIMD and FP source register.
Hm
Is the 16-bit name of the second SIMD and FP source register.
V
Is a width specifier, and can be either S or D.
d
Is the number of the SIMD and FP destination register.
n
Is the number of the first SIMD and FP source register.
m
Is the number of the second SIMD and FP source register.

Architectures supported (scalar)

Supported in the Arm®v8.2 architecture and later.

Usage

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD and FP register, from the corresponding floating-point values in the elements of the first source SIMD and FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.