17.16 LDAXR

Load-Acquire Exclusive Register.

Syntax

LDAXR Wt, [Xn|SP{,#0}] ; 32-bit

LDAXR Xt, [Xn|SP{,#0}] ; 64-bit

Where:

Wt
Is the 32-bit name of the general-purpose register to be transferred.
Xt
Is the 64-bit name of the general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load-Acquire Exclusive Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.