13.117 SHSUB8

Signed halving parallel byte-wise subtraction.

Syntax

SHSUB8{cond} {Rd}, Rn, Rm

where:

cond

is an optional condition code.

Rd

is the destination register.

Rm, Rn

are the general-purpose registers holding the operands.

Operation

This instruction subtracts each byte of the second operand from the corresponding byte of the first operand, halves the results, and writes the results into the corresponding bytes of the destination. This cannot cause overflow.

Register restrictions

You cannot use PC for any operand.

You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.

Condition flags

This instruction does not affect the N, Z, C, V, Q, or GE flags.

Availability

The 32-bit instruction is available in A32 and T32.

For the Armv7‑M architecture, the 32-bit T32 instruction is only available in an Arm®v7E-M implementation.

There is no 16-bit version of this instruction in T32.

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