20.262 URSHR (vector)

Unsigned Rounding Shift Right (immediate).


URSHR Vd.T, Vn.T, #shift


Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be one of the values shown in Usage.
Is the name of the SIMD and FP source register.
Is the right shift amount, in the range 1 to the element width in bits, and can be one of the values shown in Usage.


Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see 20.267 USHR (vector).

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-110 URSHR (Vector) specifier combinations

T shift
8B 1 to 8
16B 1 to 8
4H 1 to 16
8H 1 to 16
2S 1 to 32
4S 1 to 32
2D 1 to 64
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