17.38 LDRH (immediate)

Load Register Halfword (immediate).

Syntax

LDRH Wt, [Xn|SP], #simm ; Post-index general registers

LDRH Wt, [Xn|SP, #simm]! ; Pre-index general registers

LDRH Wt, [Xn|SP{, #pimm}] ; Unsigned offset general registers

Where:

simm
Is the signed immediate byte offset, in the range -256 to 255.
pimm
Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0.
Wt
Is the 32-bit name of the general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load Register Halfword (immediate) loads a halfword from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, and particularly LDRH (immediate).
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