17.9 LDAPR

Load-Acquire RCpc Register.

Syntax

LDAPR Wt, [Xn|SP {,#0}] ; 32-bit

LDAPR Xt, [Xn|SP {,#0}] ; 64-bit

Where:

Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xt
Is the 64-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Architectures supported

This instruction is supported in the Arm®v8.3-A architecture and later. It is optionally supported in the Armv8.2-A architecture with the RCpc extension.

Usage

Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, except that:

  • There is no ordering requirement, separate from the requirements of a Load-Acquirepc or a Store-Release, created by having a Store-Release followed by a Load-Acquirepc instruction.
  • The reading of a value written by a Store-Release by a Load-Acquirepc instruction by the same observer does not make the write of the Store-Release globally observed.

This difference in memory ordering is not described in the pseudocode.

For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

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