17.43 LDRSH (register)

Load Register Signed Halfword (register).

Syntax

LDRSH Wt, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 32-bit

LDRSH Xt, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 64-bit

Where:

Wt
Is the 32-bit name of the general-purpose register to be transferred.
Xt
Is the 64-bit name of the general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Wm
When "option<0>" is set to 0, is the 32-bit name of the general-purpose index register.
Xm
When "option<0>" is set to 1, is the 64-bit name of the general-purpose index register.
extend
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when amount is omitted, and can be one of the values shown in Usage.
amount
Is the index shift amount, optional only when extend is not LSL. Where it is permitted to be optional, it defaults to #0. It is, and can be either #0 or #1.

Usage

Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it, and writes it to a register. For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

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