17.15 LDAXP

Load-Acquire Exclusive Pair of Registers.

Syntax

LDAXP Wt1, Wt2, [Xn|SP{,#0}] ; 32-bit

LDAXP Xt1, Xt2, [Xn|SP{,#0}] ; 64-bit

Where:

Wt1
Is the 32-bit name of the first general-purpose register to be transferred.
Wt2
Is the 32-bit name of the second general-purpose register to be transferred.
Xt1
Is the 64-bit name of the first general-purpose register to be transferred.
Xt2
Is the 64-bit name of the second general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load-Acquire Exclusive Pair of Registers derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. A 32-bit pair requires the address to be doubleword aligned and is single-copy atomic at doubleword granularity. A 64-bit pair requires the address to be quadword aligned and is single-copy atomic for each doubleword at doubleword granularity. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile. For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile, and particularly LDAXP.
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