18.28 FMINNM (scalar)

Floating-point Minimum Number (scalar).

Syntax

FMINNM Hd, Hn, Hm ; Half-precision

FMINNM Sd, Sn, Sm ; Single-precision

FMINNM Dd, Dn, Dm ; Double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Hn
Is the 16-bit name of the first SIMD and FP source register.
Hm
Is the 16-bit name of the second SIMD and FP source register.
Sd
Is the 32-bit name of the SIMD and FP destination register.
Sn
Is the 32-bit name of the first SIMD and FP source register.
Sm
Is the 32-bit name of the second SIMD and FP source register.
Dd
Is the 64-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register.
Dm
Is the 64-bit name of the second SIMD and FP source register.

Operation

Floating-point Minimum Number (scalar). This instruction compares the first and second source SIMD and FP register values, and writes the smaller of the two floating-point values to the destination SIMD and FP register.

NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result that is placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vd = minNum(Vn, Vm).

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