15.11 VDIV

Floating-point divide.


VDIV{cond}.F32 {Sd}, Sn, Sm

VDIV{cond}.F64 {Dd}, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the result and operands.

Dd, Dn, Dm

are the double-precision registers for the result and operands.


The VDIV instruction divides the value in the first operand register by the value in the second operand register, and places the result in the destination register.

Floating-point exceptions

VDIV operations can produce Division by Zero, Invalid Operation, Overflow, Underflow, or Inexact exceptions.

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