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Home > A64 SIMD Vector Instructions > FRINTX (vector) |
Floating-point Round to Integral exact, using current rounding mode (vector).
FRINTX
Vd
.T
, Vn
.T
; Half-precision
FRINTX
Vd
.T
, Vn
.T
; Single-precision and double-precision
Where:
T
Is an arrangement specifier:
4H
or 8H
.
2S
, 4S
or 2D
.
Vd
Vn
Supported in the Arm^{®}v8.2 architecture and later.
Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD and FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD and FP destination register.
An Inexact exception is raised when the result value is not numerically equal to the input value. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm^{®} Architecture Reference Manual Arm^{®}v8, for Arm^{®}v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.