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Home > A64 SIMD Vector Instructions > SQDMLSL, SQDMLSL2 (vector, by element) |
Signed saturating Doubling Multiply-Subtract Long (by element).
SQDMLSL{2}
Vd
.Ta
, Vn
.Tb
, Vm
.Ts
[index
]
Where:
2
Vd
Ta
4S
or 2D
.
Vn
Tb
Vm
Is the name of the second SIMD and FP source register:
Ts
is H
, then Vm
must be in the range V0 to V15.
Ts
is S
, then Vm
must be in the range V0 to V31.
Ts
H
or S
.
index
Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD and FP register by the specified vector element of the second source SIMD and FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD and FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.
If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
The SQDMLSL
instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2
instruction extracts vector elements from the upper half of the first source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-59 SQDMLSL{2} (Vector) specifier combinations
<Q> | Ta |
Tb |
Ts |
index |
---|---|---|---|---|
- | 4S | 4H | H | 0 to 7 |
2 | 4S | 8H | H | 0 to 7 |
- | 2D | 2S | S | 0 to 3 |
2 | 2D | 4S | S | 0 to 3 |