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Home > A64 SIMD Scalar Instructions > SQRDMLSH (scalar) |
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector).
SQRDMLSH
V
d
, V
n
, V
m
Where:
V
H
or S
.
d
n
m
Supported in the Arm^{®}v8.1 architecture and later.
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector). This instruction multiplies the vector elements of the first source SIMD and FP register with the corresponding vector elements of the second source SIMD and FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD and FP register. The results are rounded.
If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.