19.115 USRA (scalar)

Unsigned Shift Right and Accumulate (immediate).


USRA Vd, Vn, #shift


Is a width specifier, D.
Is the number of the SIMD and FP destination register.
Is the number of the first SIMD and FP source register.
Is the right shift amount, in the range 1 to 64.


Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD and FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see 19.111 URSRA (scalar).

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.