20.98 FSUB (vector)

Floating-point Subtract (vector).

Syntax

FSUB Vd.T, Vn.T, Vm.T ; Half-precision

FSUB Vd.T, Vn.T, Vm.T ; Single-precision and double-precision

Where:

T

Is an arrangement specifier:

Half-precision
Can be one of 4H or 8H.
Single-precision and double-precision
Can be one of 2S, 4S or 2D.
Vd
Is the name of the SIMD and FP destination register.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in the Arm®v8.2 architecture and later.

Usage

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD and FP register, from the corresponding elements in the vector in the first source SIMD and FP register, places each result into elements of a vector, and writes the vector to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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