15.3 VADD (floating-point)

Floating-point add.


VADD{cond}.F32 {Sd}, Sn, Sm

VADD{cond}.F64 {Dd}, Dn, Dm



is an optional condition code.

Sd, Sn, Sm

are the single-precision registers for the result and operands.

Dd, Dn, Dm

are the double-precision registers for the result and operands.


The VADD instruction adds the values in the operand registers and places the result in the destination register.

Floating-point exceptions

The VADD instruction can produce Invalid Operation, Overflow, or Inexact exceptions.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.