17.5 CASPA, CASPAL, CASP, CASPL, CASPAL, CASP, CASPL

Compare and Swap Pair of words or doublewords in memory.

Syntax

CASPA Ws, <W(s+1)>, Wt, <W(t+1)>, [Xn|SP{,#0}] ; 32-bit, acquire general registers

CASPAL Ws, <W(s+1)>, Wt, <W(t+1)>, [Xn|SP{,#0}] ; 32-bit, acquire and release general registers

CASP Ws, <W(s+1)>, Wt, <W(t+1)>, [Xn|SP{,#0}] ; 32-bit, no memory ordering general registers

CASPL Ws, <W(s+1)>, Wt, <W(t+1)>, [Xn|SP{,#0}] ; 32-bit, release general registers

CASPA Xs, <X(s+1)>, Xt, <X(t+1)>, [Xn|SP{,#0}] ; 64-bit, acquire general registers

CASPAL Xs, <X(s+1)>, Xt, <X(t+1)>, [Xn|SP{,#0}] ; 64-bit, acquire and release general registers

CASP Xs, <X(s+1)>, Xt, <X(t+1)>, [Xn|SP{,#0}] ; 64-bit, no memory ordering general registers

CASPL Xs, <X(s+1)>, Xt, <X(t+1)>, [Xn|SP{,#0}] ; 64-bit, release general registers

Where:

Ws
Is the 32-bit name of the first general-purpose register to be compared and loaded.
<W(s+1)>
Is the 32-bit name of the second general-purpose register to be compared and loaded.
Wt
Is the 32-bit name of the first general-purpose register to be conditionally stored.
<W(t+1)>
Is the 32-bit name of the second general-purpose register to be conditionally stored.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xs
Is the 64-bit name of the first general-purpose register to be compared and loaded.
<X(s+1)>
Is the 64-bit name of the second general-purpose register to be compared and loaded.
Xt
Is the 64-bit name of the first general-purpose register to be conditionally stored.
<X(t+1)>
Is the 64-bit name of the second general-purpose register to be conditionally stored.

Architectures supported

Supported in the Arm®v8.1 architecture and later.

Usage

Compare and Swap Pair of words or doublewords in memory reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes.

  • CASPA and CASPAL load from memory with acquire semantics.
  • CASPL and CASPAL store to memory with release semantics.
  • CAS has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

For information about memory accesses see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.

If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is Ws and <W(s+1)>, or Xs and <X(s+1)>, are restored to the values held in the registers before the instruction was executed.

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