|Home > Overview of the Armv8 Architecture > Floating-point hardware|
There are several floating-point architecture versions and variants.
The floating-point hardware, together with associated support code, provides single-precision and double-precision floating-point arithmetic, as defined by IEEE Std. 754‑2008 IEEE Standard for Floating-Point Arithmetic. This document is referred to as the IEEE 754 standard.
The floating-point hardware uses a register bank that is distinct from the Arm® core register bank.
In AArch32 state, floating-point support is largely unchanged from VFPv4, apart from the addition of a few instructions for compliance with the IEEE 754 standard.
The floating-point architecture in AArch64 state is also based on VFPv4. The main differences are the following:
Some new instructions have been added, including: