2.6 Floating-point hardware

There are several floating-point architecture versions and variants.

The floating-point hardware, together with associated support code, provides single-precision and double-precision floating-point arithmetic, as defined by IEEE Std. 754‑2008 IEEE Standard for Floating-Point Arithmetic. This document is referred to as the IEEE 754 standard.

The floating-point hardware uses a register bank that is distinct from the Arm® core register bank.

Note:

The floating-point register bank is shared with the SIMD register bank.

In AArch32 state, floating-point support is largely unchanged from VFPv4, apart from the addition of a few instructions for compliance with the IEEE 754 standard.

The floating-point architecture in AArch64 state is also based on VFPv4. The main differences are the following:

  • In AArch64 state, the number of 128-bit SIMD and floating-point registers increases from sixteen to thirty-two.
  • Single-precision registers are no longer packed into double-precision registers, so register Sx is Dx[31:0].
  • The presence of floating-point hardware is mandated, so software floating-point linkage is not supported.
  • Earlier versions of the floating-point architecture, for instance VFPv2, VFPv3, and VFPv4, are not supported in AArch64 state.
  • VFP vector mode is not supported in either AArch32 or AArch64 state. Use Advanced SIMD instructions for vector floating-point.
  • Some new instructions have been added, including:

    • Direct conversion between half-precision and double-precision.
    • Load and store pair, replacing load and store multiple.
    • Fused multiply-add and multiply-subtract.
    • Instructions for IEEE 754-2008 compatibility.
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