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Home > A32 and T32 Instructions > LDR (register-relative) |
Load register. The address is an offset from a base register.
LDR
{
}{type
}{cond
.W
}
, Rt
label
LDRD
{
}
cond
, Rt
,
Rt2
; Doubleword label
where:
type
can be any one of:
B
SB
LDR
only. Sign extend to 32
bits.)H
SH
LDR
only. Sign extend to 32
bits.)-
cond
.W
Rt
Rt2
label
is a symbol defined by the FIELD
directive. label
specifies an offset from the base register which is defined using the MAP
directive.
label
must be within a limited distance of the value in the base
register.
The assembler calculates the offset from the base register for you.
The assembler generates an error if
is out of range.label
The following table shows the possible offsets between the label and the current instruction:
Table 13-13 Register-relative offsets
Instruction | Offset range |
---|---|
A32 LDR , LDRB
a |
±4095 |
A32 LDRSB , LDRH , LDRSH |
±255 |
A32 LDRD |
±255 |
T32, 32-bit LDR , LDRB , LDRSB , LDRH , LDRSH
a
|
-255 to 4095 |
T32, 32-bit LDRD |
±1020 b |
T32, 16-bit LDR
c |
0 to 124 b |
T32, 16-bit LDRH
c |
0 to 62 d |
T32, 16-bit LDRB
c |
0 to 31 |
T32, 16-bit LDR , base register is SP e |
0 to 1020 b |
You can use the .W
width specifier
to force LDR
to generate a 32-bit instruction in
T32 code. LDR.W
always generates a 32-bit
instruction, even if the target could be reached using a 16-bit LDR
.
For forward references, LDR
without .W
always generates a 16-bit instruction
in T32 code, even if that results in failure for a target that could be reached
using a 32-bit T32 LDR
instruction.
For 32-bit T32 instructions, you must not specify SP or PC for
either
or
Rt
.Rt2
For A32 instructions:
Rt
must be an even-numbered register.Rt
must not be LR.R12
for
Rt
.Rt2
must be R(t
+ 1)
.You can use PC for R
in word instructions. Other uses of PC
are not permitted in these instructions.t
In A32 code, you can use SP for R
in word instructions. You can use SP
for t
R
in
non-word A32 instructions but this is deprecated. t
In T32 code, you can use SP for R
in word instructions only. All other
use of SP for t
R
in these instructions are not permitted in T32 code.t
For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In Arm®v4, bits[1:0] of the address loaded must be 0b00. In Armv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in T32 state, otherwise execution continues in A32 state.
Must be a multiple of 4.
Rt and base register must be in the range R0-R7.
Must be a multiple of 2.
Rt must be in the range R0-R7.