Arm Compiler armasm User Guide : 13.53 LDR (register-relative)

13.53 LDR (register-relative)

Load register. The address is an offset from a base register.

Syntax

LDR{type}{cond}{.W} Rt, label

LDRD{cond} Rt, Rt2, label ; Doubleword

where:

type

can be any one of:

B: unsigned Byte (Zero extend to 32 bits on loads.)
SB: signed Byte (LDR only. Sign extend to 32 bits.)
H: unsigned Halfword (Zero extend to 32 bits on loads.)
SH: signed Halfword (LDR only. Sign extend to 32 bits.)
-: omitted, for Word.

cond

is an optional condition code.

.W

is an optional instruction width specifier.

Rt

is the register to load or store.

Rt2

is the second register to load or store.

label

is a symbol defined by the FIELD directive. label specifies an offset from the base register which is defined using the MAP directive.

label must be within a limited distance of the value in the base register.

Offset range and architectures

The assembler calculates the offset from the base register for you. The assembler generates an error if label is out of range.

The following table shows the possible offsets between the label and the current instruction:

Table 13-13 Register-relative offsets

Instruction	Offset range
A32 `LDR`, `LDRB` ^a	±4095
A32 `LDRSB`, `LDRH`, `LDRSH`	±255
A32 `LDRD`	±255
T32, 32-bit `LDR`, `LDRB`, `LDRSB`, `LDRH`, `LDRSH` ^a	-255 to 4095
T32, 32-bit `LDRD`	±1020 ^b
T32, 16-bit `LDR` ^c	0 to 124 ^b
T32, 16-bit `LDRH` ^c	0 to 62 ^d
T32, 16-bit `LDRB` ^c	0 to 31
T32, 16-bit `LDR`, base register is SP ^e	0 to 1020 ^b

LDR (register-relative) in T32

You can use the .W width specifier to force LDR to generate a 32-bit instruction in T32 code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in T32 code, even if that results in failure for a target that could be reached using a 32-bit T32 LDR instruction.

Doubleword register restrictions

For 32-bit T32 instructions, you must not specify SP or PC for either Rt or Rt2.

For A32 instructions:

Rt must be an even-numbered register.
Rt must not be LR.
Arm strongly recommends that you do not use R12 for Rt.
Rt2 must be R(t + 1).

Use of PC

You can use PC for Rt in word instructions. Other uses of PC are not permitted in these instructions.

Use of SP

In A32 code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word A32 instructions but this is deprecated.

In T32 code, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in T32 code.

Related concepts

12.5 Register-relative and PC-relative expressions

8.15 Address alignment in A32/T32 code

Related references

21.29 FIELD

21.52 MAP

7.11 Condition code suffixes

For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In Arm^®v4, bits[1:0] of the address loaded must be 0b00. In Armv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in T32 state, otherwise execution continues in A32 state.

Must be a multiple of 4.

Rt and base register must be in the range R0-R7.

Must be a multiple of 2.

Rt must be in the range R0-R7.

Non-Confidential	PDF version	DUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.