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Home > A64 SIMD Vector Instructions > SQRDMLSH (vector, by element) |
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).
SQRDMLSH
Vd
.T
, Vn
.T
, Vm
.Ts
[index
]
Where:
Vd
T
Vn
Vm
Is the name of the second SIMD and FP source register:
Ts
is H
, then Vm
must be in the range V0 to V15.
Ts
is S
, then Vm
must be in the range V0 to V31.
Ts
H
or S
.
index
Supported in the Arm^{®}v8.1 architecture and later.
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD and FP register with the value of a vector element of the second source SIMD and FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD and FP register. The results are rounded.
If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-65 SQRDMLSH (Vector) specifier combinations
T |
Ts |
index |
---|---|---|
4H | H | 0 to 7 |
8H | H | 0 to 7 |
2S | S | 0 to 3 |
4S | S | 0 to 3 |