15.13 VJCVT

Javascript Convert to signed fixed-point, rounding toward Zero.


VJCVT{q}.S32.F64 Sd, Dm ; A1 FP/SIMD registers (A32)

VJCVT{q}.S32.F64 Sd, Dm ; T1 FP/SIMD registers (T32)


Is an optional instruction width specifier. See 13.2 Instruction width specifiers.
Is the 32-bit name of the SIMD and FP destination register.
Is the 64-bit name of the SIMD and FP source register.

Architectures supported

Supported in the Arm®v8.3-A architecture and later.


Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD and FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and write the result to the general-purpose destination register. If the result is too large to be held as a 32-bit signed integer, then the result is the integer modulo 232, as held in a 32-bit signed integer.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.