8.4 Built-in variables and constants

armasm defines built-in variables that hold information about, for example, the state of armasm, the command-line options used, and the target architecture or processor.

The following table lists the built-in variables defined by armasm:

Table 8-1 Built-in variables

{ARCHITECTURE}

Holds the name of the selected Arm® architecture.

{AREANAME} Holds the name of the current AREA.
{ARMASM_VERSION}

Holds an integer that increases with each version of armasm. The format of the version number is Mmmuuxx where:

  • M is the major version number, 6.
  • mm is the minor version number.
  • uu is the update number.
  • xx is reserved for Arm internal use. You can ignore this for the purposes of checking whether the current release is a specific version or within a range of versions.

Note:

The built-in variable|ads$version| is deprecated.
|ads$version| Has the same value as {ARMASM_VERSION}.

{CODESIZE}

Is a synonym for {CONFIG}.

{COMMANDLINE} Holds the contents of the command line.

{CONFIG}

Has the value:

  • 64 if the assembler is assembling A64 code.
  • 32 if the assembler is assembling A32 code.
  • 16 if the assembler is assembling T32 code.

{CPU}

Holds the name of the selected processor. The value of {CPU} is derived from the value specified in the --cpu option on the command line.

{ENDIAN}

Has the value "big" if the assembler is in big-endian mode, or "little" if it is in little-endian mode.

{FPU} Holds the name of the selected FPU. The default in AArch32 state is "FP-ARMv8". The default in AArch64 state is "A64".
{INPUTFILE} Holds the name of the current source file.
{INTER} Has the Boolean value True if --apcs=/inter is set. The default is {False}.
{LINENUM} Holds an integer indicating the line number in the current source file.
{LINENUMUP} When used in a macro, holds an integer indicating the line number of the current macro. The value is the same as {LINENUM} when used in a non-macro context.
{LINENUMUPPER} When used in a macro, holds an integer indicating the line number of the top macro. The value is the same as {LINENUM} when used in a non-macro context.

{OPT}

Value of the currently-set listing option. You can use the OPT directive to save the current listing option, force a change in it, or restore its original value.

{PC} or .

Address of current instruction.

{PCSTOREOFFSET}

Is the offset between the address of the STR PC,[...] or STM Rb,{..., PC} instruction and the value of PC stored out. This varies depending on the processor or architecture specified.

{ROPI} Has the Boolean value {True} if --apcs=/ropi is set. The default is {False}.
{RWPI} Has the Boolean value {True} if --apcs=/rwpi is set. The default is {False}.

{VAR} or @

Current value of the storage area location counter.

You can use built-in variables in expressions or conditions in assembly source code. For example:

        IF {ARCHITECTURE} = "8-A"

They cannot be set using the SETA, SETL, or SETS directives.

The names of the built-in variables can be in uppercase, lowercase, or mixed, for example:

        IF {CpU} = "Generic ARM"

Note:

All built-in string variables contain case-sensitive values. Relational operations on these built-in variables do not match with strings that contain an incorrect case. Use the command-line options --cpu and --fpu to determine valid values for {CPU}, {ARCHITECTURE}, and {FPU}.

The assembler defines the built-in Boolean constants TRUE and FALSE.

Table 8-2 Built-in Boolean constants

{FALSE} Logical constant false.
{TRUE} Logical constant true.

The following table lists the target processor-related built-in variables that are predefined by the assembler. Where the value field is empty, the symbol is a Boolean value and the meaning column describes when its value is {TRUE}.

Table 8-3 Predefined macros

Name Value Meaning
{TARGET_ARCH_AARCH32} boolean {TRUE} when assembling for AArch32 state. {FALSE} when assembling for AArch64 state.
{TARGET_ARCH_AARCH64} boolean {TRUE} when assembling for AArch64 state. {FALSE} when assembling for AArch32 state.
{TARGET_ARCH_ARM} num The number of the A32 base architecture of the target processor irrespective of whether the assembler is assembling for A32 or T32. The value is defined as zero when assembling for A64, and eight when assembling for A32/T32.
{TARGET_ARCH_THUMB} num

The number of the T32 base architecture of the target processor irrespective of whether the assembler is assembling for A32 or T32. The value is defined as zero when assembling for A64, and five when assembling for A32/T32.

{TARGET_ARCH_XX}

XX represents the target architecture and its value depends on the target processor:

For the Armv8 architecture:

  • If you specify the assembler option --cpu=8-A.32 or --cpu=8-A.64 then {TARGET_ARCH_8_A} is defined.
  • If you specify the assembler option --cpu=8.1-A.32 or --cpu=8.1-A.64 then {TARGET_ARCH_8_1_A} is defined.

For the Armv7 architecture, if you specify --cpu=Cortex-A8, for example, then {TARGET_ARCH_7_A} is defined.

{TARGET_FEATURE_EXTENSION_REGISTER_COUNT} num

The number of 64-bit extension registers available in Advanced SIMD or floating-point.

{TARGET_FEATURE_CLZ}

If the target processor supports the CLZ instruction.

{TARGET_FEATURE_CRYPTOGRAPHY}

If the target processor has cryptographic instructions.

{TARGET_FEATURE_DIVIDE}

If the target processor supports the hardware divide instructions SDIV and UDIV.

{TARGET_FEATURE_DOUBLEWORD}

If the target processor supports doubleword load and store instructions, for example the A32 and T32 instructions LDRD and STRD (except the Armv6‑M architecture).

{TARGET_FEATURE_DSPMUL}

If the DSP-enhanced multiplier (for example the SMLAxy instruction) is available.

{TARGET_FEATURE_MULTIPLY}

If the target processor supports long multiply instructions, for example the A32 and T32 instructions SMULL, SMLAL, UMULL, and UMLAL (that is, all architectures except the Armv6‑M architecture).

{TARGET_FEATURE_MULTIPROCESSING}

If assembling for a target processor with Multiprocessing Extensions.

{TARGET_FEATURE_NEON}

If the target processor has Advanced SIMD.

{TARGET_FEATURE_NEON_FP16}

If the target processor has Advanced SIMD with half-precision floating-point operations.

{TARGET_FEATURE_NEON_FP32}

If the target processor has Advanced SIMD with single-precision floating-point operations.

{TARGET_FEATURE_NEON_INTEGER}

If the target processor has Advanced SIMD with integer operations.

{TARGET_FEATURE_UNALIGNED}

If the target processor has support for unaligned accesses (all architectures except the Armv6‑M architecture).

{TARGET_FPU_SOFTVFP} If assembling with the option --fpu=SoftVFP.
{TARGET_FPU_SOFTVFP_VFP}

If assembling for a target processor with SoftVFP and floating-point hardware, for example --fpu=SoftVFP+FP-ARMv8.

{TARGET_FPU_VFP}

If assembling for a target processor with floating-point hardware, without using SoftVFP, for example --fpu=FP-ARMv8.

{TARGET_FPU_VFPV2} If assembling for a target processor with VFPv2.
{TARGET_FPU_VFPV3} If assembling for a target processor with VFPv3.
{TARGET_FPU_VFPV4} If assembling for a target processor with VFPv4.
{TARGET_PROFILE_A} If assembling for a Cortex®‑A profile processor, for example, if you specify the assembler option --cpu=7-A.
{TARGET_PROFILE_M} If assembling for a Cortex‑M profile processor, for example, if you specify the assembler option --cpu=7-M.
{TARGET_PROFILE_R} If assembling for a Cortex‑R profile processor, for example, if you specify the assembler option --cpu=7-R.
Non-ConfidentialPDF file icon PDF versionDUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.