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Home > A32 and T32 Instructions > BX, BXNS |
Branch and exchange instruction set and Branch and Exchange Non-secure.
BX
{
}{cond
} q
Rm
(Armv8‑M only)BXNS
{
}{cond
} q
Rm
Where:
cond
cond
is not available on all forms of this instruction.q
Rm
The BX
instruction causes a branch to
the address contained in
and exchanges the instruction set, if necessary. The Rm
BX
instruction can change the instruction set.
BX
derives the target instruction set from bit[0] of Rm
:Rm
Rm
is 0, the processor changes to, or remains in, A32
state.Rm
is 1, the processor changes to, or remains in, T32
state.BX
to change between AArch32 and AArch64 state. The only way to change
execution state is by a change of exception level.BX
can also be used for an exception return.
The BXNS
instruction causes a branch to an address and instruction set specified by
a register, and causes a transition from the Secure to the Non-secure domain. This variant
of the instruction must only be used when additional steps required to make such a
transition safe are taken.
The following table shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.
Table 13-7 BX instruction availability and range
Instruction | A32 | T32, 16-bit encoding | T32, 32-bit encoding |
---|---|---|---|
BX Rm
|
Available | Available | Use 16-bit |
BX{cond} Rm
|
Available | - | - |
BXNS
|
- | Available | - |
You can use PC for R
in the A32 m
BX
instruction, but
this is deprecated. You cannot use PC in other A32 instructions.
You can use PC for R
in the T32 m
BX
and BXNS
instructions. You cannot use PC in other T32
instructions.
You can use SP for R
in the A32 m
BX
instruction but
this is deprecated.
You can use SP for R
in the T32 m
BX
and BXNS
instructions, but this is deprecated.
These instructions do not change the flags.
See the preceding table for details of availability of the BX
and BXNS
instructions in
both instruction sets.