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Home > A64 Data Transfer Instructions > LDTRSH |
Load Register Signed Halfword (unprivileged).
LDTRSH
Wt
, [Xn|SP
{, #simm
}] ; 32-bit
LDTRSH
Xt
, [Xn|SP
{, #simm
}] ; 64-bit
Where:
Wt
Xt
Xn|SP
simm
Load Register Signed Halfword (unprivileged) loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset.
The memory is restricted as if execution is at EL0 when:
Otherwise, the access permission is for the Exception level at which the instruction is executed. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.