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Home > A64 SIMD Scalar Instructions > SRSHL (scalar) |
Signed Rounding Shift Left (register).
SRSHL
V
d
, V
n
, V
m
Where:
V
D
.
d
n
m
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD and FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register.
If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see 19.94 SSHL (scalar).
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.