13.21 BLX, BLXNS

Branch with Link and exchange instruction set and Branch with Link and Exchange (Non-secure).

Syntax

BLX{cond}{q} label

BLX{cond}{q} Rm

BLXNS{cond}{q} Rm (Armv8‑M only)

Where:

cond
Is an optional condition code. cond is not available on all forms of this instruction.
q
Is an optional instruction width specifier. Must be set to .W when label is used.
label
Is a PC-relative expression.
Rm
Is a register containing an address to branch to.

Operation

The BLX instruction causes a branch to label, or to the address contained in Rm. In addition:

  • The BLX instruction copies the address of the next instruction into LR (R14, the link register).
  • The BLX instruction can change the instruction set.

    BLX label always changes the instruction set. It changes a processor in A32 state to T32 state, or a processor in T32 state to A32 state.

    BLX Rm derives the target instruction set from bit[0] of Rm:

    • If bit[0] of Rm is 0, the processor changes to, or remains in, A32 state.
    • If bit[0] of Rm is 1, the processor changes to, or remains in, T32 state.

Note:

  • There are no equivalent instructions to BLX to change between AArch32 and AArch64 state. The only way to change execution state is by a change of exception level.
  • Armv8‑M, Armv7‑M, and Armv6‑M only support the T32 instruction set. An attempt to change the instruction execution state causes the processor to take an exception on the instruction at the target address.

The BLXNS instruction calls a subroutine at an address and instruction set specified by a register, and causes a transition from the Secure to the Non-secure domain. This variant of the instruction must only be used when additional steps required to make such a transition safe are taken.

Instruction availability and branch ranges

The following table shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.

Table 13-6 BLX instruction availability and range

Instruction A32 T32, 16-bit encoding T32, 32-bit encoding
BLX label ±32MB ±4MB a ±16MB
BLX Rm Available Available Use 16-bit
BLX{cond} Rm Available - -
BLXNS - Available -

Register restrictions

You can use PC for Rm in the A32 BLX instruction, but this is deprecated. You cannot use PC in other A32 instructions.

You can use PC for Rm in the T32 BLX instruction. You cannot use PC in other T32 instructions.

You can use SP for Rm in this A32 instruction but this is deprecated.

You can use SP for Rm in the T32 BLX and BLXNS instructions, but this is deprecated. You cannot use SP in the other T32 instructions.

Condition flags

These instructions do not change the flags.

Availability

See the preceding table for details of availability of the BLX and BLXNS instructions in both instruction sets.

a 

BLX label and BL label are an instruction pair.

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