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Home > A64 SIMD Vector Instructions > SQRDMULH (vector, by element) |
Signed saturating Rounding Doubling Multiply returning High half (by element).
SQRDMULH
Vd
.T
, Vn
.T
, Vm
.Ts
[index
]
Where:
Vd
T
Vn
Vm
Is the name of the second SIMD and FP source register:
Ts
is H
, then Vm
must be in the range V0 to V15.
Ts
is S
, then Vm
must be in the range V0 to V31.
Ts
H
or S
.
index
Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD and FP register by the specified vector element of the second source SIMD and FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD and FP register.
The results are rounded. For truncated results, see 20.176 SQDMULH (vector, by element).
If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-66 SQRDMULH (Vector) specifier combinations
T |
Ts |
index |
---|---|---|
4H | H | 0 to 7 |
8H | H | 0 to 7 |
2S | S | 0 to 3 |
4S | S | 0 to 3 |