14.48 VLDn (single n-element structure to one lane)

Vector Load single n-element structure to one lane.


VLDn{cond}.datatype list, [Rn{@align}]{!}

VLDn{cond}.datatype list, [Rn{@align}], Rm



must be one of 1, 2, 3, or 4.


is an optional condition code.


see the following table.


is the list of Advanced SIMD registers enclosed in braces, { and }. See the following table for options.


is the general-purpose register containing the base address. Rn cannot be PC.


specifies an optional alignment. See the following table for options.


if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads have taken place.


is a general-purpose register containing an offset from the base address. If Rm is present, the instruction updates Rn to (Rn + Rm) after using the address to access memory. Rm cannot be SP or PC.


VLDn loads one n-element structure from memory into one or more Advanced SIMD registers. Elements of the register that are not loaded are unaltered.

Table 14-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)

n datatype list a align b alignment
1 8 {Dd[x]} - Standard only
  16 {Dd[x]} @16 2-byte
  32 {Dd[x]} @32 4-byte
2 8 {Dd[x], D(d+1)[x]} @16 2-byte
  16 {Dd[x], D(d+1)[x]} @32 4-byte
    {Dd[x], D(d+2)[x]} @32 4-byte
  32 {Dd[x], D(d+1)[x]} @64 8-byte
    {Dd[x], D(d+2)[x]} @64 8-byte
3 8 {Dd[x], D(d+1)[x], D(d+2)[x]} - Standard only
  16 or 32 {Dd[x], D(d+1)[x], D(d+2)[x]} - Standard only
    {Dd[x], D(d+2)[x], D(d+4)[x]} - Standard only
4 8 {Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]} @32 4-byte
  16 {Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]} @64 8-byte
    {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]} @64 8-byte
  32 {Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]} @64 or @128 8-byte or 16-byte
    {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]} @64 or @128 8-byte or 16-byte

Every register in the list must be in the range D0-D31.


align can be omitted. In this case, standard alignment rules apply.

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