20.200 SRSHL (vector)

Signed Rounding Shift Left (register).

Syntax

SRSHL Vd.T, Vn.T, Vm.T

Where:

Vd
Is the name of the SIMD and FP destination register.
T
Is an arrangement specifier, and can be one of 8B, 16B, 4H, 8H, 2S, 4S or 2D.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.

Usage

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD and FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register.

If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see 20.203 SSHL (vector).

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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