Non-Confidential | ![]() | DUI0801J | ||
| ||||
Home > A64 General Instructions > IC |
Instruction Cache operation.
This instruction is an alias of SYS
.
The equivalent instruction is SYS #
.op1
, C7, Cm
, #op2
{, Xt
}
IC <ic_op>{,
Xt
}
Where:
<ic_op>
op1
Cm
Cm
, with m
in the range 0 to 15.op2
Xt
Instruction Cache operation. For more information, see A64 system instructions for cache maintenance in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
The following table shows the valid specifier combinations:
Table 16-8 SYS parameter values corresponding to IC operations
<ic_op> | op1 |
Cm |
op2 |
---|---|---|---|
IALLU | 0 | 5 | 0 |
IALLUIS | 0 | 1 | 0 |
IVAU | 3 | 5 | 1 |