Arm Compiler armasm User Guide : 18.34 FNEG (scalar)

18.34 FNEG (scalar)

Floating-point Negate (scalar).

Syntax

FNEG Hd, Hn ; Half-precision

FNEG Sd, Sn ; Single-precision

FNEG Dd, Dn ; Double-precision

Where:

Hd: Is the 16-bit name of the SIMD and FP destination register.
Hn: Is the 16-bit name of the SIMD and FP source register.
Sd: Is the 32-bit name of the SIMD and FP destination register.
Sn: Is the 32-bit name of the SIMD and FP source register.
Dd: Is the 64-bit name of the SIMD and FP destination register.
Dn: Is the 64-bit name of the SIMD and FP source register.

Operation

Floating-point Negate (scalar). This instruction negates the value in the SIMD and FP source register and writes the result to the SIMD and FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vd = -Vn.

Related references

18.1 A64 floating-point instructions in alphabetical order

Non-Confidential	PDF version	DUI0801J
Copyright © 2014–2017, 2019 Arm Limited or its affiliates. All rights reserved.